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path: root/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
Commit message (Expand)AuthorAgeFilesLines
* [RISCV] Support named operands for CSR instructions.Ana Pazos2018-10-041-1/+1
* Test commit: fix punctuationChih-Mao Chen2018-08-141-1/+1
* [RISCV] Tail calls don't need to save return addressSameer AbuAsal2018-06-211-2/+6
* [RISCV] Support linker relax function call from auipc and jalr to jalShiva Chen2018-05-241-1/+10
* [RISCV] Lower the tail pseudoinstructionMandeep Singh Grang2018-05-231-7/+7
* Support: Simplify endian stream interface. NFCI.Peter Collingbourne2018-05-181-4/+4
* [RISCV] Implement MC layer support for the tail pseudoinstructionMandeep Singh Grang2018-05-171-2/+3
* [RISCV] Support "call" pseudoinstruction in the MC layerShiva Chen2018-04-251-0/+50
* [RISCV][NFC] Make logic in RISCVMCCodeEmitter::getImmOpValue more defensiveAlex Bradbury2018-02-221-5/+13
* [RISCV] Add support for %pcrel_lo.Ahmed Charles2018-02-061-0/+5
* [RISCV] MC layer support for the jump/branch instructions of the RVC extensionAlex Bradbury2017-12-071-0/+4
* [RISCV] MC layer support for load/store instructions of the C (compressed) ex...Alex Bradbury2017-12-071-3/+19
* [RISCV] Prepare for the use of variable-sized register classesAlex Bradbury2017-10-191-1/+1
* [RISCV] Add common fixups and relocationsAlex Bradbury2017-09-281-6/+52
* [RISCV] Add support for disassemblyAlex Bradbury2017-09-171-0/+20
* [RISCV] Add support for all RV32I instructionsAlex Bradbury2017-09-171-0/+19
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* [RISCV] Add bare-bones RISC-V MCTargetDescAlex Bradbury2016-11-011-0/+91
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