| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Tablegen-driven Instruction Compression. | Sameer AbuAsal | 2018-04-06 | 1 | -2/+14 |
| * | [RISCV] Pass MCSubtargetInfo to print methods. | Ana Pazos | 2018-01-12 | 1 | -2/+6 |
| * | [RISCV] Enable emission of alias instructions by default | Alex Bradbury | 2017-12-15 | 1 | -3/+1 |
| * | [RISCV] Implement assembler pseudo instructions for RV32I and RV64I | Alex Bradbury | 2017-12-12 | 1 | -1/+10 |
| * | [RISCV] MC layer support for the standard RV32F instruction set extension | Alex Bradbury | 2017-12-07 | 1 | -1/+11 |
| * | [RISCV] Add support for all RV32I instructions | Alex Bradbury | 2017-09-17 | 1 | -0/+14 |
| * | [RISCV] Trivial whitespace fix in RISCVInstPrinter | Alex Bradbury | 2017-08-20 | 1 | -1/+1 |
| * | [RISCV] Add RISCVInstPrinter and basic MC assembler tests | Alex Bradbury | 2017-08-15 | 1 | -0/+55 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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