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* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-3/+4
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [RISCV] Implement c.lui immediate operand constraintShiva Chen2018-02-221-0/+11
| | | | | | | | | | | | Implement c.lui immediate constraint to [1, 31] and [0xfffe0, 0xfffff]. The RISC-V ISA describes the constraint as [1, 63], with that value being loaded in to bits 17-12 of the destination register and sign extended from bit 17. Therefore, this 6-bit immediate can represent values in the ranges [1, 31] and [0xfffe0, 0xfffff]. Differential Revision: https://reviews.llvm.org/D42834 llvm-svn: 325792
* [RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming ↵Alex Bradbury2017-12-131-6/+8
| | | | | | | | | | | | | | convention When an instruction mnemonic contains a '.', we usually name the instruction with a _ in that place. e.g. fadd.s -> FADD_S. This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP. Also includes some minor formatting changes in RISCVInstrInfoC.td to better align it with the formatting conventions in the rest of the backend. llvm-svn: 320560
* [RISCV] MC layer support for the remaining RVC instructionsAlex Bradbury2017-12-131-14/+66
| | | | | | | | Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
* [RISCV] MC layer support for load/store instructions of the C (compressed) ↵Alex Bradbury2017-12-071-13/+49
| | | | | | | | | | extension Differential Revision: https://reviews.llvm.org/D40001 Patch by Shiva Chen. llvm-svn: 320037
* [RISCV] MC layer support for the standard RV32D instruction set extensionAlex Bradbury2017-12-071-0/+25
| | | | | | | | | | | As the FPR32 and FPR64 registers have the same names, use validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an FPR64 when necessary. The rest of this patch is very similar to the RV32F patch. Differential Revision: https://reviews.llvm.org/D39895 llvm-svn: 320023
* [RISCV] MC layer support for the standard RV32F instruction set extensionAlex Bradbury2017-12-071-0/+25
| | | | | | | | | | | | | The most interesting part of this patch is probably the handling of rounding mode arguments. Sadly, the RISC-V assembler handles floating point rounding modes as a special "argument" when it would be more consistent to handle them like the atomics, opcode suffixes. This patch supports parsing this optional parameter, using InstAlias to allow parsing these floating point instructions when no rounding mode is specified. Differential Revision: https://reviews.llvm.org/D39893 llvm-svn: 320020
* [RISCV][NFC] Remove unnecessary {} around single statement if blockAlex Bradbury2017-11-211-2/+1
| | | | | | | Almost too trivial to worry about, but it seems worth having consistency with upcoming commits. llvm-svn: 318760
* [RISCV] Prepare for the use of variable-sized register classesAlex Bradbury2017-10-191-8/+8
| | | | | | | | | | While parameterising by XLen, also take the opportunity to clean up the formatting of the RISCV .td files. This commit unifies the in-tree code with my patchset at <https://github.com/lowrisc/riscv-llvm>. llvm-svn: 316159
* [RISCV] Add support for disassemblyAlex Bradbury2017-09-171-0/+135
This Disassembly support allows for 'round-trip' testing, and rv32i-valid.s has been updated appropriately. Differential Revision: https://reviews.llvm.org/D23567 llvm-svn: 313486
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