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* R600/SI: Handle sign_extend and zero_extend to i64 with patterns.Matt Arsenault2014-06-103-42/+36
| | | | llvm-svn: 210563
* SelectionDAG: Expand SELECT_CC to SELECT + SETCCTom Stellard2014-06-102-19/+4
| | | | | | | | This consolidates code from the Hexagon, R600, and XCore targets. No functionality change intended. llvm-svn: 210539
* R600/SI: Rename VOP3 helper class to be more generalMatt Arsenault2014-06-092-4/+4
| | | | | | It has other uses besides shift instructions. llvm-svn: 210478
* R600/SI: Keep 64-bit not on SALUMatt Arsenault2014-06-093-10/+69
| | | | llvm-svn: 210476
* R600: Fix selection failure for vector bswapMatt Arsenault2014-06-091-0/+1
| | | | llvm-svn: 210475
* R600/SI: Match rsq instructionsMatt Arsenault2014-06-051-2/+6
| | | | llvm-svn: 210226
* Use nullptrMatt Arsenault2014-06-051-3/+2
| | | | llvm-svn: 210222
* Fix typosMatt Arsenault2014-06-032-8/+8
| | | | llvm-svn: 210135
* R600: Set all float vector expands in the same placeMatt Arsenault2014-06-011-5/+2
| | | | llvm-svn: 209988
* R600/SI: Remove redundant patternsMatt Arsenault2014-05-311-14/+0
| | | | | | These patterns are already handled in the instruction definition. llvm-svn: 209979
* R600/SI: Fix [s|u]int_to_fp for i1Matt Arsenault2014-05-312-0/+22
| | | | llvm-svn: 209971
* R600/SI: Fix pattern variable names.Matt Arsenault2014-05-291-2/+2
| | | | | | | These are confusing enough since the order swaps, so give them more useful names. llvm-svn: 209787
* R600: Add definition for flat address space ID.Matt Arsenault2014-05-222-4/+5
| | | | | | | | Use 4 since that's probably what it will be for spir. Move ADDRESS_NONE to the end to keep the constant_buffer_* values unchanged, since apparently a bunch of r600 tests use those directly. llvm-svn: 209463
* R600: Try to convert BFE back to standard bit ops when possible.Matt Arsenault2014-05-221-0/+21
| | | | | | | This allows existing DAG combines to work on them, and then we can re-match to BFE if necessary during instruction selection. llvm-svn: 209462
* R600: Add dag combine for BFEMatt Arsenault2014-05-223-2/+78
| | | | llvm-svn: 209461
* R600: Implement ComputeNumSignBitsForTargetNode for BFEMatt Arsenault2014-05-222-0/+30
| | | | llvm-svn: 209460
* R600: Implement computeMaskedBitsForTargetNode for BFEMatt Arsenault2014-05-221-1/+29
| | | | llvm-svn: 209459
* R600: Expand mul24 for GPUs without itMatt Arsenault2014-05-224-13/+25
| | | | llvm-svn: 209458
* R600: Expand mad24 for GPUs without itMatt Arsenault2014-05-224-1/+24
| | | | llvm-svn: 209457
* R600: Add intrinsics for mad24Matt Arsenault2014-05-227-3/+41
| | | | llvm-svn: 209456
* R600/SI: Move instruction pattern to instruction definitionMatt Arsenault2014-05-221-6/+3
| | | | llvm-svn: 209454
* R600/SI: Match fp_to_uint / uint_to_fp for f64Matt Arsenault2014-05-221-2/+7
| | | | llvm-svn: 209388
* R600: Add comment describing problems with LowerConstantInitializerMatt Arsenault2014-05-211-0/+10
| | | | llvm-svn: 209333
* R600: Partially fix constant initializers for structs and vectors.Matt Arsenault2014-05-211-6/+33
| | | | | | | This should extend the current workaround to work with structs that only contain legal, scalar types. llvm-svn: 209331
* Use cast<> instead of unchecked dyn_castMatt Arsenault2014-05-211-1/+1
| | | | llvm-svn: 209310
* Remove unused method declarationMatt Arsenault2014-05-191-1/+0
| | | | llvm-svn: 209174
* Resolving MSVC warnings about switch statements with a default label, but no ↵Aaron Ballman2014-05-191-4/+2
| | | | | | case labels. No functional changes intended. llvm-svn: 209126
* R600/SI: Refactor the VOP3_32 tablegen classTom Stellard2014-05-166-34/+112
| | | | | | | | This will allow us to use a single MachineInstr to represent instructions which behave the same but have different encodings on some subtargets. llvm-svn: 209028
* R600/SI: Add a PredicateControl class for managing TableGen predicatesTom Stellard2014-05-163-28/+22
| | | | | | This was inspired by the PredicateControl class in the MIPS backend. llvm-svn: 209027
* R600/SI: Move tablegen patterns away from instruction defsTom Stellard2014-05-161-30/+31
| | | | llvm-svn: 209026
* R600/SI: Remove unused instructionTom Stellard2014-05-161-7/+0
| | | | llvm-svn: 209025
* R600/SI: Promote f32 SELECT to i32Tom Stellard2014-05-162-6/+2
| | | | llvm-svn: 209024
* R600/SI: Remove duplicate patternTom Stellard2014-05-161-5/+0
| | | | llvm-svn: 209023
* Use range forMatt Arsenault2014-05-154-62/+45
| | | | llvm-svn: 208922
* R600/SI: Stop using VSrc_* as the default register class for types.Tom Stellard2014-05-152-63/+11
| | | | | | | | | | We now use SReg_* for integer types and VReg_* for floating-point types. This should help simplify the SIFixSGPRCopies pass and no longer causes ISel to insert a COPY after termiator instuctions that output a value. This change is covered by exisitng tests. llvm-svn: 208888
* R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-05-152-7/+28
| | | | | | This prevents a future commit from regressing the load-i1.ll test. llvm-svn: 208887
* R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0Tom Stellard2014-05-151-5/+6
| | | | llvm-svn: 208886
* R600/SI: Use VALU instructions for i1 opsTom Stellard2014-05-152-11/+29
| | | | llvm-svn: 208885
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-142-19/+19
| | | | | | inappropriate since it lost its Mask parameter in r154011. llvm-svn: 208811
* R600/SI: Try to fix BFE operands when moving to VALUMatt Arsenault2014-05-131-1/+1
| | | | | | This was broken by r208479 llvm-svn: 208740
* Use cast<> for unchecked useMatt Arsenault2014-05-121-1/+1
| | | | llvm-svn: 208627
* Use cast<> for unchecked useMatt Arsenault2014-05-121-2/+2
| | | | llvm-svn: 208618
* Use range forMatt Arsenault2014-05-122-6/+4
| | | | llvm-svn: 208617
* R600: Add mul24 intrinsicsMatt Arsenault2014-05-123-4/+10
| | | | llvm-svn: 208604
* Fix return before elseMatt Arsenault2014-05-111-18/+18
| | | | llvm-svn: 208510
* R600/SI: Fold fabs/fneg into src input modifierVincent Lejeune2014-05-101-2/+31
| | | | llvm-svn: 208480
* R600/SI: Prettier display of input modifiersVincent Lejeune2014-05-107-38/+77
| | | | llvm-svn: 208479
* R600/SI: Use pseudo instruction for fabs/clamp/fnegVincent Lejeune2014-05-102-4/+74
| | | | llvm-svn: 208478
* R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructionsTom Stellard2014-05-091-4/+35
| | | | llvm-svn: 208432
* R600/SI: Fix SMRD pattern for offsets > 32 bitsTom Stellard2014-05-092-7/+6
| | | | | | We were dropping the high bits of 64-bit immediate offsets. llvm-svn: 208431
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