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* R600: Implement 64bit SHLJan Vesely2014-06-182-0/+42
| | | | | | | v2: Use c++ style comment Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211157
* R600/SI: Make sure target flags are set on pseudo VOP3 instructionsTom Stellard2014-06-172-14/+14
| | | | llvm-svn: 211120
* R600/SI: Match cttz_zero_undefMatt Arsenault2014-06-172-1/+6
| | | | llvm-svn: 211116
* R600/SI: Match ctlz_zero_undefMatt Arsenault2014-06-173-3/+8
| | | | llvm-svn: 211115
* R600: Use LDS and vectors for private memoryTom Stellard2014-06-1717-18/+661
| | | | llvm-svn: 211110
* R600/SI: Add a pattern for llvm.AMDGPU.barrier.globalTom Stellard2014-06-173-1/+16
| | | | llvm-svn: 211109
* SelectionDAG: Expand i64 = FP_TO_SINT i32Tom Stellard2014-06-171-0/+1
| | | | llvm-svn: 211108
* R600/SI: Re-initialize the m0 register after using it for indirect addressingTom Stellard2014-06-171-37/+50
| | | | | | | | | | | | We need to store a value greater than or equal to the number of LDS bytes allocated by the shader in the m0 register in order for LDS instructions to work correctly. We always initialize m0 at the beginning of a shader, but this register is also used for indirect addressing offsets, so we need to re-initialize it any time we use indirect addressing. llvm-svn: 211107
* Fix copy paste errorMatt Arsenault2014-06-151-1/+1
| | | | llvm-svn: 211003
* R600: Remove a few more things from AMDILISelLoweringMatt Arsenault2014-06-152-27/+21
| | | | | | | Try to keep all the setOperationActions for integer ops together. llvm-svn: 211001
* R600: Fix assert on vector sdivMatt Arsenault2014-06-151-4/+4
| | | | llvm-svn: 211000
* R600: Move / cleanup more leftover AMDIL stuff.Matt Arsenault2014-06-153-71/+30
| | | | llvm-svn: 210998
* R600: Move division custom lowering out of AMDILISelLoweringMatt Arsenault2014-06-153-271/+257
| | | | llvm-svn: 210997
* R600: Report that integer division is expensive.Matt Arsenault2014-06-151-0/+7
| | | | | | Divides by weird constants now emit much better code. llvm-svn: 210995
* R600: Remove dead codeMatt Arsenault2014-06-152-75/+11
| | | | llvm-svn: 210994
* Fix typoMatt Arsenault2014-06-141-1/+1
| | | | llvm-svn: 210968
* R600: Fix asserts related to constant initializersMatt Arsenault2014-06-141-5/+20
| | | | | | | | | | | This would assert if a constant address space was extern and therefore didn't have an initializer. If the initializer was undef, it would hit the unreachable unhandled initializer case. An extern global should never really occur since we don't have machine linking, but bugpoint likes to remove initializers. llvm-svn: 210967
* R600: Use address space enum instead of valueMatt Arsenault2014-06-141-6/+7
| | | | llvm-svn: 210966
* R600: Cleanup some old AMDIL stuff.Matt Arsenault2014-06-132-95/+42
| | | | | | | | | | | | Move / delete some of the more obviously wrong setOperationAction calls. Most of these are setting Expand for types that aren't legal which is the default anyway. Leave stuff that might require more thought on whether it's junk or not as it is. No functionality change. llvm-svn: 210922
* R600: Remove AMDIL instruction and register definitionsTom Stellard2014-06-1321-447/+104
| | | | | | Most of these are no longer used any more. llvm-svn: 210915
* R600: Don't call setOperationAction with things that aren't opcodes.Matt Arsenault2014-06-131-8/+0
| | | | | | | | | CondCode actions are set with setCondCodeAction. This should have been a harmless bug since the values seem to only collide only with nodes that don't need to be handled, and these are already correctly setup elsewhere. llvm-svn: 210888
* R600/SI: Fix selection error on i64 rotl / rotr.Matt Arsenault2014-06-132-6/+7
| | | | | | Evergreen is still broken due to missing shl_parts. llvm-svn: 210885
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-1323-43/+54
| | | | llvm-svn: 210869
* R600: Drop use of cached TargetMachine in R600InstrInfo.cppTom Stellard2014-06-131-1/+2
| | | | llvm-svn: 210868
* R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cppTom Stellard2014-06-131-1/+1
| | | | llvm-svn: 210865
* R600: Mostly remove remaining AMDIL intrinsics.Matt Arsenault2014-06-128-240/+32
| | | | | | | | | Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. llvm-svn: 210827
* R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*Matt Arsenault2014-06-122-41/+29
| | | | | | | There is not such thing as a 0-data ds instruction, and the data operand needs to be a vgpr set to something meaningful. llvm-svn: 210756
* R600: Set correct InstrItinClass for instructions using *Helper classesTom Stellard2014-06-111-3/+3
| | | | | | | | | We weren't doing this before, so all instruction using the *Helper classes were considered for any ALU slot. This fixes a hang in the builtin-char-clz-1.0.generated.cl piglit test. llvm-svn: 210703
* R600: BCNT_INT is a vector only instructionTom Stellard2014-06-111-1/+1
| | | | llvm-svn: 210702
* R600/SI: Fix bitcast between v2i32 and f64Matt Arsenault2014-06-111-0/+2
| | | | | | | | | | This is the same problem fixed in r210664 for more types. The test passes without this fix. For some reason I'm only hitting this when creating selects lowered to v2i32 selects. llvm-svn: 210692
* R600/SI: Update place using old subtarget predicateMatt Arsenault2014-06-111-2/+2
| | | | llvm-svn: 210683
* R600/SI: Add common 64-bit LDS atomicsMatt Arsenault2014-06-113-17/+43
| | | | llvm-svn: 210680
* R600/SI: Add instruction definitions for 64-bit LDS atomicsMatt Arsenault2014-06-111-0/+47
| | | | llvm-svn: 210679
* R600/SI: Add 32-bit LDS atomic cmpxchgMatt Arsenault2014-06-112-0/+24
| | | | llvm-svn: 210678
* R600/SI: Use LDS atomic inc / decMatt Arsenault2014-06-111-0/+16
| | | | llvm-svn: 210677
* R600/SI: Add other LDS atomic operationsMatt Arsenault2014-06-111-3/+12
| | | | llvm-svn: 210676
* R600/SI: Add instruction definitions for more LDS opsMatt Arsenault2014-06-112-0/+104
| | | | llvm-svn: 210675
* R600/SI: Fix backwards names for local atomic instructions.Matt Arsenault2014-06-111-4/+4
| | | | | | | The manual lists them as *_RTN_U32, not *_U32_RTN, which is more consistent with how every other sized instruction is named. llvm-svn: 210674
* R600/SI: Refactor local atomics.Matt Arsenault2014-06-112-11/+30
| | | | | | | Use patterns that will also match the immediate offset to match the normal read / writes. llvm-svn: 210673
* R600/SI: Use v_cvt_f32_ubyte* instructionsMatt Arsenault2014-06-117-5/+170
| | | | | | | This eliminates extra extract instructions when loading an i8 vector to a float vector. llvm-svn: 210666
* R600/SI: Fix selection failure on scalar_to_vectorMatt Arsenault2014-06-112-6/+23
| | | | | | | | | | | There seem to be only 2 places that produce these, and it's kind of tricky to hit them. Also fixes failure to bitcast between i64 and v2f32, although this for some reason wasn't actually broken in the simple bitcast testcase, but did in the scalar_to_vector one. llvm-svn: 210664
* Try to fix the msvc build.Rafael Espindola2014-06-111-1/+2
| | | | llvm-svn: 210636
* Use cast instead of assert + dyn_castMatt Arsenault2014-06-111-3/+2
| | | | llvm-svn: 210628
* R600: Add helper functions.Matt Arsenault2014-06-112-0/+21
| | | | | | | Extract these from some of my other patches, since this is the only thing really making them dependent on each other. llvm-svn: 210627
* R600/SI: Emit an error when attempting to spill VGPRs v4Tom Stellard2014-06-101-10/+24
| | | | | | | | | | | | | | | | | | I can't get VGPR spilling to work reliable, so for now just emit an error when the register allocator tries to spill VGPRs. v2: - Fix build v3: - Added crash fix when spilling SPGRs v4: - Use V_MOV_B32 as a dummy instruction instead of S_NOP Patch by: Darren Powell https://bugs.freedesktop.org/show_bug.cgi?id=75276 llvm-svn: 210588
* R600/SI: Fix a crash when spilling SGPRsTom Stellard2014-06-102-11/+8
| | | | | | | | | | | We need to make sure only one new instruction is added when spilling otherwise the register allocator may crash. This fixes a crash in the game Antichamber. https://bugs.freedesktop.org/show_bug.cgi?id=75276 llvm-svn: 210587
* R600: Use BCNT_INT for evergreenMatt Arsenault2014-06-104-5/+16
| | | | llvm-svn: 210569
* R600/SI: Implement i64 ctpopMatt Arsenault2014-06-105-1/+64
| | | | llvm-svn: 210568
* R600/SI: Use bcnt instruction for ctpopMatt Arsenault2014-06-106-11/+27
| | | | llvm-svn: 210567
* R600: Handle fcopysignMatt Arsenault2014-06-105-3/+27
| | | | llvm-svn: 210564
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