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* R600: Don't crash on unhandled instruction in promote allocaMatt Arsenault2014-06-271-2/+24
| | | | llvm-svn: 211906
* Fix missing newline and simplify debug printing.Matt Arsenault2014-06-271-5/+5
| | | | llvm-svn: 211850
* R600: Move load/store ReplaceNodeResults to common code.Matt Arsenault2014-06-272-14/+14
| | | | | | Future patches will want to custom lower loads on SI. llvm-svn: 211848
* R600/SI: Add FP mode bits to binary.Matt Arsenault2014-06-263-14/+128
| | | | | | | | The default rounding mode to initialize the mode register needs to be reported to the runtime. Fill in other bits a kernel may be interested in setting for future use. llvm-svn: 211791
* Silencing a warning about isZExtFree hiding an inherited virtual function. ↵Aaron Ballman2014-06-262-0/+5
| | | | | | No functional change intended. llvm-svn: 211783
* R600: Fix vector FMAMatt Arsenault2014-06-261-0/+1
| | | | llvm-svn: 211757
* R600/SI: Use a ComplexPattern for MUBUF storesTom Stellard2014-06-243-36/+67
| | | | | | | | Now that non-leaf ComplexPatterns are allowed we can fold all the MUBUF store patterns into the instruction definition. We will also be able to reuse this new ComplexPattern for MUBUF loads and atomic operations. llvm-svn: 211644
* R600: Promote i64 stores to v2i32Tom Stellard2014-06-243-3/+10
| | | | | | Now we need only one 64-bit pattern for stores. llvm-svn: 211643
* R600: Fix inconsistency in rsq instructions.Matt Arsenault2014-06-248-14/+55
| | | | | | | | | | | | | R600 was using a clamped version of rsq, but SI was not. Add a new rsq_clamped intrinsic and use them consistently. It's unclear to me from the documentation what behavior the R600 instructions have, so I assume they have the legacy behavior described by the SI documents. For R600, use RECIPSQRT_IEEE for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also has RECIPSQRT_FF, which I'm not sure how it fits in here. llvm-svn: 211637
* R600: Remove DIV_INFMatt Arsenault2014-06-242-3/+2
| | | | | | | This corresponded to an amdil instruction which there is a 2 instruction equivalent for. llvm-svn: 211616
* R600/SI: Move pattern to instruction definitionMatt Arsenault2014-06-241-6/+1
| | | | llvm-svn: 211614
* R600/SI: Verify restrictions on div_scale operands.Matt Arsenault2014-06-231-0/+35
| | | | llvm-svn: 211524
* R600/SI: Fix div_scale intrinsic.Matt Arsenault2014-06-234-4/+62
| | | | | | | The operand that must match one of the others does matter, and implement selecting for it. llvm-svn: 211523
* R600: Remove AMDILISelLoweringMatt Arsenault2014-06-236-48/+13
| | | | llvm-svn: 211519
* R600: Select is not expensive.Matt Arsenault2014-06-231-0/+7
| | | | llvm-svn: 211518
* R600: Move add/sub with overflow out of AMDILISelLoweringMatt Arsenault2014-06-233-19/+12
| | | | | | Add more tests for these. llvm-svn: 211517
* R600: Move more out of AMDILISelLoweringMatt Arsenault2014-06-233-37/+19
| | | | llvm-svn: 211516
* R600: Don't set fp_round_inreg action.Matt Arsenault2014-06-231-9/+0
| | | | | | | There's no point in setting this since it seems to only by created in 1 place for ppcf128 llvm-svn: 211515
* R600/SI: Handle i64 sub.Matt Arsenault2014-06-234-13/+25
| | | | | | We can handle it the same way as add llvm-svn: 211514
* R600/SI: Move selection of i64 add to separate function.Matt Arsenault2014-06-231-39/+43
| | | | | | Also don't use a SmallVector for fixed size array. llvm-svn: 211513
* R600: Rename AMDIL fileMatt Arsenault2014-06-237-38/+33
| | | | llvm-svn: 211512
* Fix missing words in sentenceMatt Arsenault2014-06-231-3/+3
| | | | llvm-svn: 211511
* Use helper functionMatt Arsenault2014-06-231-7/+2
| | | | llvm-svn: 211510
* Alphabetize forward declarationsMatt Arsenault2014-06-231-2/+2
| | | | llvm-svn: 211509
* R600: Use LowerSDIVREM for i64 node replaceJan Vesely2014-06-223-92/+120
| | | | | | | | v2: move div/rem node replacement to R600ISelLowering make lowerSDIVREM protected Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211478
* R600: Implement custom SDIVREM.Jan Vesely2014-06-222-4/+44
| | | | | | | | | | Instead of separate SDIV/SREM. SDIV used UDIV which in turn used UDIVREM anyway. SREM used SDIV(UDIV->UDIVREM)+MUL+SUB, using UDIVREM directly is more efficient. v2: Don't use all caps names Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211477
* R600/SI: Add patterns for ctpop inside a branchTom Stellard2014-06-201-12/+38
| | | | llvm-svn: 211378
* R600/SI: Add a pattern for f32 ftruncTom Stellard2014-06-203-5/+4
| | | | llvm-svn: 211377
* R600: Expand vector flog2Tom Stellard2014-06-201-0/+1
| | | | llvm-svn: 211376
* R600: Expand vector fexp2Tom Stellard2014-06-201-0/+1
| | | | llvm-svn: 211375
* R600/SI: SI Control Flow Annotation bug fixedTom Stellard2014-06-201-25/+21
| | | | | | | | | | | | Mixing of AddAvailableValue and GetValueAtEndOfBlock methods of SSAUpdater leaded to the endless loop generation when the nested loops annotated. This fixes a bug in the OCL_ML/KNN OpenCV test. The test case is too complex for FileCheck and would be very fragile. Patch by: Elena Denisova llvm-svn: 211374
* R600/SI: Add a VALU pattern for i64 xorTom Stellard2014-06-201-4/+7
| | | | llvm-svn: 211373
* R600: Trivial subtarget feature cleanups.Matt Arsenault2014-06-202-11/+5
| | | | | | | Remove an unused AMDIL leftover, correct extra periods appearing in the help menu. llvm-svn: 211341
* Fix typosAlp Toker2014-06-191-1/+1
| | | | llvm-svn: 211304
* Convert some assert(0) to llvm_unreachable or fold an 'if' condition into ↵Craig Topper2014-06-191-9/+5
| | | | | | the assert. llvm-svn: 211254
* R600/SI: Add intrinsics for various math instructions.Matt Arsenault2014-06-198-13/+113
| | | | | | | | These will be used for custom lowering and for library implementations of various math functions, so it's useful to expose these as builtins. llvm-svn: 211247
* Use stdint macros for specifying size of constantsMatt Arsenault2014-06-181-2/+3
| | | | llvm-svn: 211231
* R600: Handle fnearbyintMatt Arsenault2014-06-182-0/+13
| | | | | | | | The difference from rint isn't really relevant here, so treat them as equivalent. OpenCL doesn't have nearbyint, so this is sort of pointless other than for completeness. llvm-svn: 211229
* R600/SI: add gather4 and getlod intrinsics (v3)Marek Olsak2014-06-184-26/+175
| | | | | | | | | This contains all the previous patches + getlod support on top of it. It doesn't use SDNodes anymore, so it's quite small. It also adds v16i8 to SReg_128, which is used for the sampler descriptor. Reviewed-by: Tom Stellard llvm-svn: 211228
* Use LL suffix for literal that should be 64-bits.Matt Arsenault2014-06-181-1/+1
| | | | | | This hopefully fixes Windows llvm-svn: 211225
* R600: Expand vector fceilJan Vesely2014-06-181-0/+1
| | | | | | | | | Move fp64 fceil tests to fceil64.ll v2: rebase Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211194
* Work around ridiculous warning.Matt Arsenault2014-06-181-2/+5
| | | | | | Apparently C++ doesn't really have hex floating point constants. llvm-svn: 211192
* R600/SI: Add intrinsics for brev instructionsMatt Arsenault2014-06-186-1/+12
| | | | llvm-svn: 211187
* R600/SI: Prettier operand printing for 64-bit ops.Matt Arsenault2014-06-182-14/+17
| | | | | | Copy what is done for 32-bit already so the order is about the same. llvm-svn: 211186
* R600: Implement f64 ftrunc, ffloor and fceil.Matt Arsenault2014-06-182-0/+111
| | | | | | CI has instructions for these, so this fixes them for older hardware. llvm-svn: 211183
* R600: Custom lower f64 frint for pre-CIMatt Arsenault2014-06-182-0/+27
| | | | llvm-svn: 211182
* R600/SI: Temporary fix for f64 fnegMatt Arsenault2014-06-181-0/+4
| | | | | | | This should be a source modifier, but this unblocks most of my math patches. llvm-svn: 211181
* R600/SI: Comparisons set vcc.Matt Arsenault2014-06-182-105/+115
| | | | llvm-svn: 211178
* R600: Implement 64bit SRAJan Vesely2014-06-181-5/+7
| | | | | | | v2: Use capitalized variable name Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211159
* R600: Implement 64bit SRLJan Vesely2014-06-182-0/+41
| | | | | | | v2: use C++ style comment Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211158
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