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* R600: Remove unused includeMatt Arsenault2014-08-041-1/+0
| | | | llvm-svn: 214728
* R600/SI: Fix extra whitespace in asm strMatt Arsenault2014-08-031-1/+1
| | | | | | | | | This slipped in in r214467, so something like V_MOV_B32_e32 v0, ... is now printed with 2 spaces between the instruction name and first operand. llvm-svn: 214660
* R600/SI: Fix formatting.Matt Arsenault2014-08-021-22/+28
| | | | | | Avoid weird line wrapping of BuildMI dest register. llvm-svn: 214608
* [SDAG] MorphNodeTo recursively deletes dead operands of the oldChandler Carruth2014-08-011-1/+3
| | | | | | | | | | | | | fromulation of the node, which isn't really the desired behavior from within the combiner or legalizer, but is necessary within ISel. I've added a hopefully helpful comment and fixed the only two places where this took place. Yet another step toward the combiner and legalizer not needing to use update listeners with virtual calls to manage the worklists behind legalization and combining. llvm-svn: 214574
* Revert "R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cpp"Tom Stellard2014-08-012-42/+37
| | | | | | | | This reverts commit r214566. I did not mean to commit this yet. llvm-svn: 214572
* R600/SI: Remove leftover debugging codeTom Stellard2014-08-011-2/+0
| | | | llvm-svn: 214569
* R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cppTom Stellard2014-08-012-37/+42
| | | | | | | SI doesn't use REGISTER_LOAD anymore, but it was still hitting this code path for 8-bit and 16-bit private loads. llvm-svn: 214566
* R600/SI: Don't display GDS bit for read2Matt Arsenault2014-08-011-1/+1
| | | | | | | This isn't displayed for any other instructions anymore, and isn't ever used. llvm-svn: 214523
* R600/SI: Fix build warningTom Stellard2014-08-011-1/+1
| | | | llvm-svn: 214475
* R600/SI: Do abs/neg folding with ComplexPatternsTom Stellard2014-08-0111-658/+1034
| | | | | | | | | | Abs/neg folding has moved out of foldOperands and into the instruction selection phase using complex patterns. As a consequence of this change, we now prefer to select the 64-bit encoding for most instructions and the modifier operands have been dropped from integer VOP3 instructions. llvm-svn: 214467
* R600/SI: Simplify and fix handling of VOP2 in SIInstrInfo::legalizeOperandsTom Stellard2014-08-012-28/+53
| | | | | | | | | | | | We were incorrectly assuming that all VOP2 instructions can read SGPRs in Src0, but this is not true for instructions that read carry-in from VCC. The old logic has been replaced with new logic which checks the defined register classes of the VOP2 instruction to determine whether or not to legalize the operands. llvm-svn: 214465
* R600/SI: Fold immediates when shrinking instructionsTom Stellard2014-08-013-12/+79
| | | | | | | This will prevent us from using extra MOV instructions once we prefer selecting 64-bit instructions. llvm-svn: 214464
* R600/SI: Fix incorrect commute operation in shrink instructions passTom Stellard2014-08-013-3/+16
| | | | | | | | We were commuting the instruction by still shrinking it using the original opcode. NOTE: This is a candidate for the 3.5 branch. llvm-svn: 214463
* Make sure no loads resulting from load->switch DAGCombine are marked invariantLouis Gerbarg2014-07-312-4/+5
| | | | | | | | | | | | | | Currently when DAGCombine converts loads feeding a switch into a switch of addresses feeding a load the new load inherits the isInvariant flag of the left side. This is incorrect since invariant loads can be reordered in cases where it is illegal to reoarder normal loads. This patch adds an isInvariant parameter to getExtLoad() and updates all call sites to pass in the data if they have it or false if they don't. It also changes the DAGCombine to use that data to make the right decision when creating the new load. llvm-svn: 214449
* R600/SI: Remove redundant setting of bits on instructions.Matt Arsenault2014-07-301-13/+2
| | | | | | | | neverHasSideEffects is deprecated, and hasSideEffects = 0 is already set on the base classes of the basic ALU instruction classes. The base classes also already set mayLoad = 0 and mayStore = 0 llvm-svn: 214283
* R600/SI: Consider adjacent offsets in getLdStBaseRegImmOfsMatt Arsenault2014-07-301-13/+39
| | | | | | | | | We can treat ds_read2_* as a single offset if the offsets are adjacent. No test since emission of read2 instructions for partially aligned loads isn't implemented yet. llvm-svn: 214269
* R600/SI: Implement getLdStBaseRegImmOfsMatt Arsenault2014-07-292-0/+62
| | | | llvm-svn: 214225
* R600/SI: Enable named operand table for DS instructionsMatt Arsenault2014-07-291-0/+1
| | | | llvm-svn: 214217
* Remove line with no effectMatt Arsenault2014-07-291-1/+0
| | | | llvm-svn: 214216
* R600/SI: Add isMUBUF / isMTBUFMatt Arsenault2014-07-294-1/+21
| | | | | | Also add missing comments about how the flags work. llvm-svn: 214195
* R600/SI: Set bits on SMRD instructionsMatt Arsenault2014-07-291-0/+3
| | | | | | Set mayStore = 0 and enable named operand table. llvm-svn: 214194
* Fix typos / grammar.Matt Arsenault2014-07-291-1/+1
| | | | llvm-svn: 214147
* Fix header including itselfMatt Arsenault2014-07-291-3/+2
| | | | llvm-svn: 214146
* R600/SI: Fix return type for isMIMG / isSMRDMatt Arsenault2014-07-282-4/+4
| | | | | | All the others use bool, so these should too. llvm-svn: 214106
* R600/SI: Implement getOptimalMemOpTypeMatt Arsenault2014-07-282-0/+26
| | | | | | | The default guess uses i32. This needs an address space argument to really do the right thing in all cases. llvm-svn: 214104
* R600/SI: Make argument loads invariantMatt Arsenault2014-07-281-9/+17
| | | | llvm-svn: 214101
* Add alignment value to allowsUnalignedMemoryAccessMatt Arsenault2014-07-272-10/+13
| | | | | | | | | | Rename to allowsMisalignedMemoryAccess. On R600, 8 and 16 byte accesses are mostly OK with 4-byte alignment, and don't need to be split into multiple accesses. Vector loads with an alignment of the element type are not uncommon in OpenCL code. llvm-svn: 214055
* R600: Move intrinsic lowering to separate functionsMatt Arsenault2014-07-262-109/+126
| | | | llvm-svn: 214023
* R600/SI: Allow partial unrolling and increase thresholds.Matt Arsenault2014-07-251-1/+7
| | | | llvm-svn: 213985
* Move R600 subtarget dependent variables onto the subtarget.Eric Christopher2014-07-256-83/+83
| | | | | | No functional change. llvm-svn: 213982
* [SDAG] Enable the new assert for out-of-range result numbers inChandler Carruth2014-07-251-2/+2
| | | | | | | | | | | | | | | | SDValues, fixing the two bugs left in the regression suite. The key for both of these was the use a single value type rather than a VTList which caused an unintentionally single-result merge-value node. Fix this by getting the appropriate VTList in place. Doing this exposed that the comments in x86's code abouth how MUL_LOHI operands are handle is wrong. The bug with the use of out-of-range result numbers was hiding the bug about the order of operands here (as best i can tell). There are more places where the code appears to get this backwards still... llvm-svn: 213931
* R600: Add FMA instructions for EvergreenMatt Arsenault2014-07-242-0/+12
| | | | llvm-svn: 213882
* R600: Add new functions for splitting vector loads and stores.Matt Arsenault2014-07-244-26/+145
| | | | | | These will be used in future patches and shouldn't change anything yet. llvm-svn: 213877
* R600: Match rcp node on pre-SIMatt Arsenault2014-07-243-1/+9
| | | | llvm-svn: 213844
* R600: Fix LowerSDIV24Matt Arsenault2014-07-241-51/+50
| | | | | | | | | | Use ComputeNumSignBits instead of checking for i8 / i16 which only worked when AMDIL was lying about having legal i8 / i16. If an integer is known to fit in 24-bits, we can do division faster with float ops. llvm-svn: 213843
* R600: Implement enableClusterLoads()Matt Arsenault2014-07-242-0/+7
| | | | llvm-svn: 213831
* R600: silence GCC warningSaleem Abdulrasool2014-07-211-0/+1
| | | | | | | | | | GCC believes it may be possible to not return a value from the switch: lib/Target/R600/SIRegisterInfo.cpp:187:1: warning: control reaches end of non-void function [-Wreturn-type] Add an unreachable label to indicate that this is not possible and still permit switch coverage checking. llvm-svn: 213572
* R600/SI: Refactor VOP3 instruction definitionsTom Stellard2014-07-212-21/+52
| | | | llvm-svn: 213571
* R600/SI: Separate encoding and operand definitions into their own classesTom Stellard2014-07-211-132/+174
| | | | llvm-svn: 213570
* R600/SI: Initailize encoding fields of unused VOP3 modifiers to 0Tom Stellard2014-07-211-0/+5
| | | | llvm-svn: 213564
* R600/SI: Initialize unused VOP3 sources to 0 instead of SIOperand.ZEROTom Stellard2014-07-211-6/+6
| | | | llvm-svn: 213563
* R600/SI: Add instruction shrinking passTom Stellard2014-07-218-0/+218
| | | | | | This pass converts 64-bit instructions to 32-bit when possible. llvm-svn: 213561
* R600/SI: VOPC instructions explicitly define VCCTom Stellard2014-07-211-1/+1
| | | | | | Therefore we don't need to add it to the implict defs list. llvm-svn: 213558
* R600/SI: Clean up some of the unused REGISTER_{LOAD,STORE} codeTom Stellard2014-07-211-148/+24
| | | | | | | | | There are a few more cleanups to do, but I ran into some problems with ext loads and trunc stores, when I tried to change some of the vector loads and stores from custom to legal, so I wasn't able to get rid of everything. llvm-svn: 213552
* R600/SI: Use scratch memory for large private arraysTom Stellard2014-07-2118-67/+450
| | | | llvm-svn: 213551
* R600/SI: Specify wavefront size for SI and CITom Stellard2014-07-211-2/+4
| | | | llvm-svn: 213550
* R600/SI: Remove vaddr operand from BUFFER_LOAD_*_OFFSET instructionsTom Stellard2014-07-212-4/+4
| | | | | | This operand is never used. llvm-svn: 213549
* R600/SI: Store constant initializer data in constant memoryTom Stellard2014-07-2116-27/+185
| | | | | | | | | | | | This implements a solution for constant initializers suggested by Vadim Girlin, where we store the data after the shader code and then use the S_GETPC instruction to compute its address. This saves use the trouble of creating a new buffer for constant data and then having to pass the pointer to the kernel via user SGPRs or the input buffer. llvm-svn: 213530
* R600/SI: Add isCFDepth0 Predicate to SALU addc patternTom Stellard2014-07-211-10/+16
| | | | llvm-svn: 213529
* R600/SI: Use VALU for i1 XORTom Stellard2014-07-212-5/+11
| | | | llvm-svn: 213528
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