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* R600/SI: Use mad for fsub + fmulMatt Arsenault2014-08-296-0/+54
| | | | | | | We can use a negate source modifier to match this for fsub. llvm-svn: 216735
* Use BitVector instead of int in R600 SIISelLowering.Alexey Samsonov2014-08-271-3/+4
| | | | | | | int may not have enough bits in it, which was detected by UBSan bootstrap (it reported left shift by a too large constant). llvm-svn: 216579
* R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops with 32-bit alignmentTom Stellard2014-08-224-2/+63
| | | | llvm-svn: 216279
* R600/SI: Use a ComplexPattern for DS loads and storesTom Stellard2014-08-223-32/+58
| | | | llvm-svn: 216278
* R600/SI: Wrap local memory pointer in AssertZExt on SITom Stellard2014-08-221-0/+12
| | | | | | | | | These pointers are really just offsets and they will always be less than 16-bits. Using AssertZExt allows us to use computeKnownBits to prove that these values are positive. We will use this information in a later commit. llvm-svn: 216277
* R600/SI: Use correct helper class for DS_WRITE2 instructionsTom Stellard2014-08-221-1/+1
| | | | | | | DS_1A uses a single offset encoding, so offset1 wasn't being encoded. llvm-svn: 216276
* name change: isPow2DivCheap -> isPow2SDivCheapSanjay Patel2014-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | isPow2DivCheap That name doesn't specify signed or unsigned. Lazy as I am, I eventually read the function and variable comments. It turns out that this is strictly about signed div. But I discovered that the comments are wrong: srl/add/sra is not the general sequence for signed integer division by power-of-2. We need one more 'sra': sra/srl/add/sra That's the sequence produced in DAGCombiner. The first 'sra' may be removed when dividing by exactly '2', but that's a special case. This patch corrects the comments, changes the name of the flag bit, and changes the name of the accessor methods. No functional change intended. Differential Revision: http://reviews.llvm.org/D5010 llvm-svn: 216237
* R600/SI: Teach moveToVALU how to handle more S_LOAD_* instructionsTom Stellard2014-08-212-9/+127
| | | | llvm-svn: 216220
* R600/SI: Make sure SCRATCH_WAVE_OFFSET is added as Live-In to the functionTom Stellard2014-08-212-9/+7
| | | | | | This fixes a crash in an ocl conformance test. llvm-svn: 216219
* R600/SI: Remove unused SGPR spilling codeTom Stellard2014-08-212-80/+0
| | | | llvm-svn: 216218
* R600/SI: Use eliminateFrameIndex() to expand SGPR spill pseudosTom Stellard2014-08-215-112/+159
| | | | | | | | | | | | | | | This will simplify the SGPR spilling and also allow us to use MachineFrameInfo for calculating offsets, which should be more reliable than our custom code. This fixes a crash in some cases where a register would be spilled in a branch such that the VGPR defined for spilling did not dominate all the uses when restoring. This fixes a crash in an ocl conformance test. The test requries register spilling and is too big to include. llvm-svn: 216217
* R600/SI: Handle VCC in SIRegisterInfo::getPhysRegSubReg()Tom Stellard2014-08-211-0/+11
| | | | | | | This fixes a crash in an ocl conformance test. The test requries register spilling and is too big to include. llvm-svn: 216216
* Cleanup: Delete seemingly unused reference to MachineDominatorTree from ↵Alexey Samsonov2014-08-201-5/+3
| | | | | | ScheduleDAGInstrs. llvm-svn: 216124
* Silencing an MSVC warning about loop variable conflicting with a variable ↵Aaron Ballman2014-08-181-1/+1
| | | | | | from an outer scope. NFC. llvm-svn: 215888
* R600/SI: Move all fabs / fneg handling to patternsMatt Arsenault2014-08-152-117/+31
| | | | llvm-svn: 215749
* R600/SI: Use source modifiers for f64 fnegMatt Arsenault2014-08-153-6/+38
| | | | llvm-svn: 215748
* R600/SI: Use source modifier for f64 fabsMatt Arsenault2014-08-152-2/+30
| | | | llvm-svn: 215747
* R600/SI: Refactor fneg / fabs patternsMatt Arsenault2014-08-151-22/+17
| | | | llvm-svn: 215746
* R600/SI: Fix offset folding in some cases with shifted pointers.Matt Arsenault2014-08-154-1/+137
| | | | | | | | | | | | | Ordinarily (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) is only done if the add has one use. If the resulting constant add can be folded into an addressing mode, force this to happen for the pointer operand. This ends up happening a lot because of how LDS objects are allocated. Since the globals are allocated next to each other, acessing the first element of the second object is directly indexed by a shifted pointer. llvm-svn: 215739
* R600/SI: Add intrinsic for ldexpMatt Arsenault2014-08-154-2/+14
| | | | llvm-svn: 215734
* R600/SI: Implement isLegalAddressingModeMatt Arsenault2014-08-152-0/+47
| | | | | | | | | | | | | The default assumes that a 16-bit signed offset is used. LDS instruction use a 16-bit unsigned offset, so it wasn't being used in some cases where it was assumed a negative offset could be used. More should be done here, but first isLegalAddressingMode needs to gain an addressing mode argument. For now, copy most of the rest of the default implementation with the immediate offset change. llvm-svn: 215732
* Remove HasLEB128.Rafael Espindola2014-08-151-1/+0
| | | | | | We already require CFI, so it should be safe to require .leb128 and .uleb128. llvm-svn: 215712
* R600: Correctly set the src value offset for scalarized kernel argsMatt Arsenault2014-08-131-11/+29
| | | | | | | | | | This for some reason fixes v1i64 kernel arguments on pre-SI. This currently breaks some other cases in the kernel-args.ll test for R600, but I'm not particularly confident in the new output. VTX_READ_* are not used for some of the scalarized cases, and the code reading from the constant buffer doesn't make much sense to me. llvm-svn: 215564
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-1327-80/+80
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* R600: Use optimized 24bit path in udivremJan Vesely2014-08-122-18/+39
| | | | | | | | | v2: drop enum keyword use correct extension mode don't bother computing the sign in unsinged case Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 215462
* R600: Remove unused code.Jan Vesely2014-08-122-174/+0
| | | | | Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 215461
* R600: Use i24 optimized path for SREMJan Vesely2014-08-122-8/+28
| | | | | | | | | v2: add tests rename LowerSDIV24 to LowerSDIVREM24 handle the rem part in this function Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 215460
* R600/SIInstrInfo.cpp: Suppress an warning. [-Wunused-variable]NAKAMURA Takumi2014-08-111-0/+1
| | | | llvm-svn: 215406
* R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variantTom Stellard2014-08-114-155/+289
| | | | | | | This saves us from having to copy a 64-bit 0 value into VGPRs for BUFFER_* instruction which only have a 12-bit immediate offset. llvm-svn: 215399
* R600/SI: Add an _OFFEN variant MUBUF_STORE_* and use it for scratch writesTom Stellard2014-08-112-23/+34
| | | | llvm-svn: 215398
* R600/SI: Clear lds bit on MUBUF instructions used for private storesTom Stellard2014-08-111-0/+1
| | | | | | | | This bit was left uninitialized, which was causing some random failures of piglit tests. NOTE: This is a candidate for the 3.5 branch. llvm-svn: 215396
* Fix typos:Sylvestre Ledru2014-08-111-1/+1
| | | | | | | * libaries => libraries * avaiable => available llvm-svn: 215366
* R600: Disable FP exceptions.Matt Arsenault2014-08-091-0/+5
| | | | llvm-svn: 215277
* R600/SI: Custom lower CONCAT_VECTORSTom Stellard2014-08-091-1/+3
| | | | | | | This will lower them using register copies rather than loads and stores to the stack. llvm-svn: 215270
* Temporarily Revert "Nuke the old JIT." as it's not quite ready toEric Christopher2014-08-071-1/+1
| | | | | | | | | | | be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 215154
* Nuke the old JIT.Rafael Espindola2014-08-071-1/+1
| | | | | | | | | I am sure we will be finding bits and pieces of dead code for years to come, but this is a good start. Thanks to Lang Hames for making MCJIT a good replacement! llvm-svn: 215111
* Remove the target machine from CCState. Previously it was only usedEric Christopher2014-08-063-16/+24
| | | | | | | | | to get the subtarget and that's accessible from the MachineFunction now. This helps clear the way for smaller changes where we getting a subtarget will require passing in a MachineFunction/Function as well. llvm-svn: 214988
* Correct commentMatt Arsenault2014-08-061-1/+1
| | | | llvm-svn: 214945
* R600: Increase nearby load scheduling threshold.Matt Arsenault2014-08-061-9/+20
| | | | | | | | | This partially fixes weird looking load scheduling in memcpy test. The load clustering doesn't seem particularly smart, but this method seems to be partially deprecated so it might not be worth trying to fix. llvm-svn: 214943
* R600/SI: Implement areLoadsFromSameBasePtrMatt Arsenault2014-08-062-0/+102
| | | | | | | | This currently has a noticable effect on the kernel argument loads. LDS and global loads are more problematic, I think because of how copies are currently inserted to ensure that the address is a VGPR. llvm-svn: 214942
* R600/SI: Add definitions for ds_read2st64_ / ds_write2st64_Matt Arsenault2014-08-051-3/+4
| | | | llvm-svn: 214936
* R600/SI: Use register class instead of list of registersMatt Arsenault2014-08-051-1/+1
| | | | | | I'm not sure if this has any consequence or not. llvm-svn: 214902
* R600/SI: Add exec_lo and exec_hi subregisters.Matt Arsenault2014-08-051-2/+10
| | | | | | | | | | | This allows accessing an SReg subregister with a normal subregister index, instead of getting a machine verifier error. Also be sure to include all of these subregisters in SReg_32. This fixes inferring SGPR instead of SReg when finding a super register class. llvm-svn: 214901
* R600/SI: Update MUBUF assembly string to match AMD proprietary compilerTom Stellard2014-08-053-21/+97
| | | | llvm-svn: 214866
* R600/SI: Avoid generating REGISTER_LOAD instructions.Tom Stellard2014-08-051-1/+2
| | | | | | | SI doesn't use REGISTER_LOAD anymore, but it was still hitting this code path for 8-bit and 16-bit private loads. llvm-svn: 214865
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-0516-46/+36
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-0425-115/+134
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* R600/SI: Fix definitions for ds_read2 / ds_write2 instructions.Matt Arsenault2014-08-042-3/+4
| | | | | | | These were just wrong, using the wrong register classes and store2 was missing an operand. llvm-svn: 214756
* Move the R600 intrinsic support back to the target machine - there'sEric Christopher2014-08-044-6/+4
| | | | | | | nothing subtarget dependent about the intrinsic support in any backend as far as I can tell. llvm-svn: 214738
* Use the known address space constant rather than checking itMatt Arsenault2014-08-041-1/+1
| | | | llvm-svn: 214729
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