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* R600: Don't set BypassSlowDiv for 64-bit divisionTom Stellard2014-09-221-3/+0
| | | | | | | | | | | | | BypassSlowDiv is used by codegen prepare to insert a run-time check to see if the operands to a 64-bit division are really 32-bit values and if they are it will do 32-bit division instead. This is not useful for R600, which has predicated control flow since both the 32-bit and 64-bit paths will be executed in most cases. It also increases code size which can lead to more instruction cache misses. llvm-svn: 218252
* R600/SI: Use ISD::MUL instead of ISD::UMULO when lowering divisionTom Stellard2014-09-221-3/+3
| | | | | | | ISD::MUL and ISD:UMULO are the same except that UMULO sets an overflow bit. Since we aren't using the overflow bit, we should use ISD::MUL. llvm-svn: 218251
* R600/SI: Add enums for some hard-coded valuesTom Stellard2014-09-224-26/+87
| | | | llvm-svn: 218250
* Fix typoMatt Arsenault2014-09-211-4/+3
| | | | llvm-svn: 218223
* Use llvm_unreachable instead of assert(!)Matt Arsenault2014-09-211-2/+2
| | | | llvm-svn: 218222
* R600/SI: Don't use strings for single charactersMatt Arsenault2014-09-211-18/+18
| | | | llvm-svn: 218221
* R600/SI: Fix config value for number of gprsTom Stellard2014-09-191-4/+7
| | | | | | | | | | | | | | In r217636, the value stored in KernelInfo.Num[VS]GPRSs was changed from the highest GPR index used to the number of gprs in order to be consistent with the name of the variable. The code writing the config values still assumed that the value in this variable was the highest GPR index used, which caused the compiler to over report the number of GPRs being used. https://bugs.freedesktop.org/show_bug.cgi?id=84089 llvm-svn: 218150
* R600: Better fix for bug 20982Matt Arsenault2014-09-191-6/+3
| | | | | | Just do the left shift as unsigned to avoid the UB. llvm-svn: 218092
* Reverting NFC changes from r218050. Instead, the warning was disabled for ↵Aaron Ballman2014-09-181-2/+0
| | | | | | GCC in r218059, so these changes are no longer required. llvm-svn: 218062
* R600: Bug 20982 - Avoid undefined left shift of negative valueMatt Arsenault2014-09-181-3/+10
| | | | | | | I'm not sure what the hardware actually does, so don't bother trying to fold it for now. llvm-svn: 218057
* Fixing a bunch of -Woverloaded-virtual warnings due to hiding ↵Aaron Ballman2014-09-181-0/+2
| | | | | | getSubtargetImpl from the base class. NFC. llvm-svn: 218050
* Add a new pass FunctionTargetTransformInfo. This pass serves as aEric Christopher2014-09-181-2/+2
| | | | | | | | | | | shim between the TargetTransformInfo immutable pass and the Subtarget via the TargetMachine and Function. Migrate a single call from BasicTargetTransformInfo as an example and provide shims where TargetMachine begins taking a Function to determine the subtarget. No functional change. llvm-svn: 218004
* R600/SI: Remove assertMatt Arsenault2014-09-171-6/+7
| | | | | | | | | | Since read2 / write2 are emitted for 4-byte aligned 8-byte accesses, these are seen by the scheduler. The DAG scheduler is semi-deprecated, so just ignore these for now. llvm-svn: 217969
* R600/SI: Rough first implementation of shouldClusterLoadsMatt Arsenault2014-09-172-0/+26
| | | | llvm-svn: 217968
* Fix float division-by-zero in R600 scheduler.Alexey Samsonov2014-09-171-14/+18
| | | | | | This bug was reported by UBSan. llvm-svn: 217967
* R600/SI: Change formatting of printed FP immediatesMatt Arsenault2014-09-171-13/+26
| | | | | | | | | | Only 1 decimal place should be printed for inline immediates. Other constants should be hex constants. Does not include f64 tests because folding those inline immediates currently does not work. llvm-svn: 217964
* R600/SI: Remove promotion of instructions to e64 forms.Matt Arsenault2014-09-172-58/+6
| | | | | | | | Instructions are now generally selected to the e64 forms originally, and shrunk down later. Rename foldOperands to legalizeOperands, since that's really most of what it tries to do. llvm-svn: 217959
* Fix typoMatt Arsenault2014-09-161-1/+1
| | | | llvm-svn: 217892
* R600/SI: Prefer selecting more e64 instruction forms.Matt Arsenault2014-09-151-7/+7
| | | | | | | | Add some more tests to make sure better operand choices are still made. Leave some cases that seem to have no reason to ever be e64 alone. llvm-svn: 217789
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-1520-11/+440
| | | | llvm-svn: 217777
* R600/SI: Fix promote alloca pass breaking addrspacecastMatt Arsenault2014-09-151-0/+7
| | | | llvm-svn: 217776
* R600/SI: Enable named operand table for MTBUFMatt Arsenault2014-09-151-0/+1
| | | | | | | There is already code trying to use it for getting the offset. llvm-svn: 217775
* Fix typoMatt Arsenault2014-09-131-4/+4
| | | | llvm-svn: 217730
* R600/SI: Fix off by 1 error in used register countMatt Arsenault2014-09-111-2/+4
| | | | | | | The register numbers start at 0, so if only 1 register was used, this was reported as 0. llvm-svn: 217636
* R600: Add cmpxchg instruction for evergreenAaron Watry2014-09-112-5/+29
| | | | | | | | | | | | | | | | | Refactored the R600_LDS_1A2D class a bit to get it to actually work. It seemed to be previously unused and broken. We also have to disable the conversion to the noret variant for now in R600ISelLowering because the getLDSNoRetOp method only handles 1A1D LDS ops. Someone can feel free to modify the AMDGPU::getLDSNoRetOp method to work for more than 1A1D variants of LDS operations. It's being left as a future TODO for now. Signed-off-by: Aaron Watry <awatry at gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217596
* R600: Add LDS_WRXCHG[_RET] instructions for Evergreen.Aaron Watry2014-09-111-0/+4
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217594
* R600: Add LDS_MIN_[U]INT[_RET] instructions for EvergreenAaron Watry2014-09-111-0/+8
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217593
* R600: Add LDS_XOR[_RET] instructions for EvergreenAaron Watry2014-09-111-0/+4
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217592
* R600: Add LDS_OR[_RET] instructions for EvergreenAaron Watry2014-09-111-0/+4
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217591
* R600: Add LDS_AND[_RET] instructions for EvergreenAaron Watry2014-09-111-0/+4
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217590
* R600: Add LDS_MAX_[U]INT[_RET] instructions for EvergreenAaron Watry2014-09-111-0/+8
| | | | | | | | | | | | | This was only present for SI before. Cayman may still be missing, but I am unable to test that currently. v2: Don't create atomicrmw max tests in separate file Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> CC: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 217589
* R600/SI: Fix losing chain when fixing reg class of loads.Matt Arsenault2014-09-101-6/+14
| | | | | | | The lost chain resulting in earlier side effecting nodes being deleted. llvm-svn: 217561
* R600/SI: Report offset in correct units for st64 DS instructionsMatt Arsenault2014-09-101-0/+15
| | | | | | | | | | | Need to convert the 64 element offset into bytes, not just the element size like the normal case instructions. Noticed by inspection. This can't be hit now because st64 instructions aren't emitted during instruction selection, and the post-RA scheduler isn't enabled. llvm-svn: 217560
* R600: Custom lower fremMatt Arsenault2014-09-102-0/+20
| | | | llvm-svn: 217553
* Rename getMaximumUnrollFactor -> getMaxInterleaveFactor; also rename option ↵Sanjay Patel2014-09-101-2/+2
| | | | | | | | | | | names controlling this variable. "Unroll" is not the appropriate name for this variable. Clang already uses the term "interleave" in pragmas and metadata for this. Differential Revision: http://reviews.llvm.org/D5066 llvm-svn: 217528
* R600/SI: Fix assertion from copying a TargetGlobalAddressMatt Arsenault2014-09-081-1/+2
| | | | | | | | | | | | | Assert in scheduler from an inserted copy_to_regclass from a constant. This only seems to break sometimes when a constant initializer address is forced into VGPRs in a non-entry block. No test since the only case I've managed to hit only happens with a future patch, and that case will also not be a problem once scalar instructions are used in non-entry blocks. llvm-svn: 217380
* R600/SI: Replace LDS atomics with no return versionsMatt Arsenault2014-09-083-19/+35
| | | | llvm-svn: 217379
* R600/SI: Add InstrMapping for noret atomics.Matt Arsenault2014-09-083-50/+78
| | | | | | | | Only handles LDS atomics for now, and will be used to replace atomics with no uses with the no return versions. llvm-svn: 217378
* R600/SI: Fix register class for some 64-bit atomicsMatt Arsenault2014-09-071-5/+5
| | | | llvm-svn: 217323
* R600/SI: Use same complex patterns for DS atomicsMatt Arsenault2014-09-051-67/+47
| | | | | | | This fixes hitting the same negative base offset problem that was already fixed for regular loads and stores. llvm-svn: 217256
* R600: Fix FROUNDJan Vesely2014-09-052-4/+7
| | | | | | | | round halfway cases away from zero Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 217250
* R600/SI: Fix bug in SIInstrInfo::legalizeOpWithMove()Tom Stellard2014-09-051-4/+5
| | | | | | | | | | We must constrain the destination register class of legalized operands to a VGPR class or else the illegal operand may be folded back into the instruction by the register coalescer. This fixes a bug in add.ll that will be uncovered by future commits. llvm-svn: 217249
* R600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of 64-bit operationsTom Stellard2014-09-053-6/+8
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=83416 llvm-svn: 217248
* R600/SI: Un-move pattern I forgot to remove in last commitMatt Arsenault2014-09-031-5/+5
| | | | llvm-svn: 217109
* R600/SI: Try to keep i32 mul on SALUMatt Arsenault2014-09-032-7/+16
| | | | | | | Also fix bug this exposed where when legalizing an immediate operand, a v_mov_b32 would be created with a VSrc dest register. llvm-svn: 217108
* R600/SI: Add a pattern for i64 and in a branchTom Stellard2014-09-031-0/+1
| | | | llvm-svn: 217041
* R600/SI: Fix typos in SIInstrInfo::areLoadsFromSameBasePtr()Tom Stellard2014-09-031-2/+2
| | | | | | | | | | This fixes a crash in the OpenCV test: ImgprocWarpResizeArea/Resize.Mat/16 There is no test case for this, because this failure depends on a specific ordering of the loads, which could easily change. llvm-svn: 217040
* Add override to overriden virtual methods, remove virtual keywords.Benjamin Kramer2014-09-038-19/+12
| | | | | | No functionality change. Changes made by clang-tidy + some manual cleanup. llvm-svn: 217028
* Reinstate "Nuke the old JIT."Eric Christopher2014-09-021-1/+1
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* Remove 'virtual' keyword from methods markedwith 'override' keyword.Craig Topper2014-08-303-10/+10
| | | | llvm-svn: 216823
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