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* R600/SI: Refactor VOP2 instruction defsTom Stellard2014-10-072-42/+46
| | | | llvm-svn: 219254
* R600/SI: Refactor VOP1 instruction defsTom Stellard2014-10-073-72/+96
| | | | llvm-svn: 219253
* R600: Remove dead codeMatt Arsenault2014-10-072-18/+1
| | | | llvm-svn: 219242
* R600: Remove some redundant initializations from AMDGPUMCAsmInfoTom Stellard2014-10-071-10/+0
| | | | llvm-svn: 219238
* R600: Use MCAsmInfoELF as AMDGPUMCAsmInfo base classTom Stellard2014-10-072-3/+8
| | | | | | | | | | | | | The main reason for this is that the MCAsmInfo class, which we were previously using as the base class, sets PrivateGlobalPrefix to "L", which causes all global functions that start with L to be treated as local symbols. MCAsmInfoELF sets PrivateGlobalPrefix to ".L", which is what we want, and it is probably a good idea to use this as the base class anyway, since we are emitting ELF binaries. llvm-svn: 219237
* R600/SI: Remove assertion in SIInstrInfo::areLoadsFromSameBasePtr()Tom Stellard2014-10-071-1/+4
| | | | | | | Added a FIXME coment instead, we need to handle the case where the two DS instructions being compared have different numbers of operands. llvm-svn: 219236
* Remove unnecessary copying or replace it with moves in a bunch of places.Benjamin Kramer2014-10-042-10/+10
| | | | | | NFC. llvm-svn: 219061
* R600/SI: Custom lower f64 -> i64 conversionsMatt Arsenault2014-10-033-3/+57
| | | | llvm-svn: 219038
* R600: Custom lower [s|u]int_to_fp for i64 -> f64Matt Arsenault2014-10-033-2/+46
| | | | llvm-svn: 219037
* R600/SI: Fix ftrunc f64 conformance failures.Matt Arsenault2014-10-031-1/+1
| | | | | | Re-add the tests since they were deleted at some point llvm-svn: 219036
* R600: Align functions to 256 bytesTom Stellard2014-10-032-3/+12
| | | | llvm-svn: 219002
* Eliminate some deep std::vector copies. NFC.Benjamin Kramer2014-10-033-6/+5
| | | | llvm-svn: 218999
* R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol ↵Tom Stellard2014-10-011-1/+1
| | | | | | table llvm-svn: 218776
* R600/SI: Add a generic pseudo EXP instructionTom Stellard2014-10-013-8/+30
| | | | llvm-svn: 218767
* R600/SI: Add generic pseudo MTBUF instructionsTom Stellard2014-10-013-31/+58
| | | | llvm-svn: 218766
* R600/SI: Add generic pseudo SMRD instructionsTom Stellard2014-10-012-14/+39
| | | | llvm-svn: 218765
* R600/SI: Fix printing of clamp and omodMatt Arsenault2014-09-304-17/+55
| | | | | | | | No tests for omod since nothing uses it yet, but this should get rid of the remaining annoying trailing zeros after some instructions. llvm-svn: 218692
* R600/SI: Update VOP3b to not include obsolete operandsMatt Arsenault2014-09-303-15/+16
| | | | | | abs / neg are now part of the srcN_modifiers operands llvm-svn: 218691
* Fix missing C++ mode commentMatt Arsenault2014-09-301-1/+1
| | | | llvm-svn: 218654
* Fix include orderMatt Arsenault2014-09-291-1/+1
| | | | llvm-svn: 218611
* R600/SI: Fix hardcoded values for modifiers.Matt Arsenault2014-09-294-19/+22
| | | | | | Move enums to SIDefines.h llvm-svn: 218610
* R600/SI: Also fix fsub + fadd a, a to mad combinesMatt Arsenault2014-09-291-0/+22
| | | | llvm-svn: 218609
* R600/SI: Fix using mad with multiplies by 2Matt Arsenault2014-09-291-0/+35
| | | | | | | | | These turn into fadds, so combine them into the target mad node. fadd (fadd (a, a), b) -> mad 2.0, a, b llvm-svn: 218608
* R600/SI: Use break instead of continueMatt Arsenault2014-09-261-1/+1
| | | | | | If an instruction doesn't have src1, it doesn't have src2 llvm-svn: 218536
* R600/SI: Add a note about the order of the operands to div_scaleMatt Arsenault2014-09-261-0/+6
| | | | llvm-svn: 218534
* R600/SI: Move finding SGPR operand to move to separate functionMatt Arsenault2014-09-262-63/+71
| | | | llvm-svn: 218533
* R600/SI Allow same SGPR to be used for multiple operandsMatt Arsenault2014-09-261-5/+32
| | | | | | | | | | | Instead of moving the first SGPR that is different than the first, legalize the operand that requires the fewest moves if one SGPR is used for multiple operands. This saves extra moves and is also required for some instructions which require that the same operand be used for multiple operands. llvm-svn: 218532
* R600/SI: Partially move operand legalization to post-isel hook.Matt Arsenault2014-09-264-70/+41
| | | | | | | | | Disable the SGPR usage restriction parts of the DAG legalizeOperands. It now should only be doing immediate folding until it can be replaced later. The real legalization work is now done by the other SIInstrInfo::legalizeOperands llvm-svn: 218531
* R600/SI: Implement findCommutedOpIndicesMatt Arsenault2014-09-262-1/+36
| | | | | | | | | | | The base implementation of commuteInstruction is used in some cases, but it turns out this has been broken for a long time since modifiers were inserted between the real operands. The base implementation of commuteInstruction also fails on immediates, which also needs to be fixed. llvm-svn: 218530
* R600/SI: Don't move operands that are required to be SGPRsMatt Arsenault2014-09-261-1/+20
| | | | | | | | e.g. v_cndmask_b32 requires the condition operand be an SGPR. If one of the source operands were an SGPR, that would be considered the one SGPR use and the condition operand would be illegally moved. llvm-svn: 218529
* R600/SI: Don't assert on exotic operand typesMatt Arsenault2014-09-261-1/+1
| | | | | | | | | This needs a test, but I'm not sure if it is currently possible and I originally hit it due to a bug. Right now the only global address operands have no reason to be VALU instructions, although it theoretically could be a problem. llvm-svn: 218528
* R600/SI: Fix using wrong operand indices when commutingMatt Arsenault2014-09-261-11/+20
| | | | | | | | | | | | | No test since the current SIISelLowering::legalizeOperands effectively hides this, and the general uses seem to only fire on SALU instructions which don't have modifiers between the operands. When trying to use legalizeOperands immediately after instruction selection, it now sees a lot more patterns it did not see before which break on this. llvm-svn: 218527
* R600/SI: Remove apparently dead code in legalizeOperandsMatt Arsenault2014-09-261-8/+0
| | | | | | | | No tests hit this, and I don't see any way a GlobalAddress node would survive beyond lowering on SI. It it would, the move should probably be inserted by selection. llvm-svn: 218526
* R600/SI: Fix emitting trailing whitespace after s_waitcntMatt Arsenault2014-09-261-5/+19
| | | | llvm-svn: 218486
* R600/SI: Add support for global atomic addTom Stellard2014-09-254-3/+111
| | | | llvm-svn: 218457
* Silencing an "enumeral and non-enumeral type in conditional expression" ↵Aaron Ballman2014-09-241-1/+2
| | | | | | warning. NFC. llvm-svn: 218381
* R600/SI: Add new helper isSGPRClassIDMatt Arsenault2014-09-242-8/+14
| | | | | | Move these into header since they are trivial llvm-svn: 218360
* R600/SI: Fix hardcoded and wrong operand numbers.Matt Arsenault2014-09-241-5/+3
| | | | | | Also fix leftover debug printing llvm-svn: 218359
* R600/SI: Enable named operand table for SALU instructionsMatt Arsenault2014-09-241-0/+8
| | | | llvm-svn: 218358
* R600/SI: Enable selecting SALU inside branchesTom Stellard2014-09-242-27/+0
| | | | | | We can do this now that the FixSGPRLiveRanges pass is working. llvm-svn: 218353
* R600/SI: Move PHIs that define SGPRs to the VALU in most casesTom Stellard2014-09-241-0/+52
| | | | | | | This fixes a bug that is uncovered by a future commit and will be tested by the test/CodeGen/R600/sgpr-control-flow.ll test case. llvm-svn: 218352
* R600/SI: Fix the FixSGPRLiveRanges passTom Stellard2014-09-244-33/+121
| | | | | | | | | | | The previous implementation was extending the live range of SGPRs by modifying the live intervals directly. This was causing a lot of machine verification errors when the machine scheduler was enabled. The new implementation adds pseudo instructions with implicit uses to extend the live ranges of SGPRs, which works much better. llvm-svn: 218351
* R600/SI: Mark EXEC_LO and EXEC_HI as reservedTom Stellard2014-09-241-0/+6
| | | | | | | These registers can be allocated and used like other 32-bit registers, but it seems like a likely source for bugs. llvm-svn: 218350
* R600/SI: Fix SIRegisterInfo::getPhysRegSubReg()Tom Stellard2014-09-241-1/+10
| | | | | | | | Correctly handle special registers: EXEC, EXEC_LO, EXEC_HI, VCC_LO, VCC_HI, and M0. The previous implementation would assertion fail when passed these registers. llvm-svn: 218349
* R600/SI: Implement VGPR register spilling for compute at -O0 v3Tom Stellard2014-09-248-48/+332
| | | | | | | | | | | | | | VGPRs are spilled to LDS. This still needs more testing, but we need to at least enable it at -O0, because the fast register allocator spills all registers that are live at the end of blocks and without this some future commits will break the flat-address-space.ll test. v2: Only calculate thread id once v3: Move insertion of spill instructions to SIRegisterInfo::eliminateFrameIndex() llvm-svn: 218348
* R600/SI: Clean up checks for legality of immediate operandsTom Stellard2014-09-238-67/+149
| | | | | | | | | | | | | | There are new register classes VCSrc_* which represent operands that can take an SGPR, VGPR or inline constant. The VSrc_* class is now used to represent operands that can take an SGPR, VGPR, or a 32-bit immediate. This allows us to have more accurate checks for legality of immediates, since before we had no way to distinguish between operands that supported any 32-bit immediate and operands which could only support inline constants. llvm-svn: 218334
* Fix typoMatt Arsenault2014-09-231-2/+3
| | | | llvm-svn: 218324
* Revert "R600/SI: Add support for global atomic add"Tom Stellard2014-09-224-111/+3
| | | | | | | | | This reverts commit r218254. The global_atomics.ll test fails with asserts disabled. For some reason, the compiler fails to produce the atomic no return variants. llvm-svn: 218257
* R600/SI: Add support for global atomic addTom Stellard2014-09-224-3/+111
| | | | llvm-svn: 218254
* R600/SI: Remove modifier operands from V_CNDMASK_B32_e64Tom Stellard2014-09-222-8/+3
| | | | | | Modifiers don't work for this instruction. llvm-svn: 218253
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