summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/R600
Commit message (Collapse)AuthorAgeFilesLines
...
* R600: Replace big texture opcode switch in scheduler by usesTC/usesVCVincent Lejeune2013-05-171-23/+3
| | | | llvm-svn: 182127
* R600: Relax some vector constraints on Dot4.Vincent Lejeune2013-05-1710-26/+280
| | | | | | | | | | Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register coalescer to remove some unneeded COPY. This patch also defines some structures/functions that can be used to handle every vector instructions (CUBE, Cayman special instructions...) in a similar fashion. llvm-svn: 182126
* R600: Improve texture handlingVincent Lejeune2013-05-1711-201/+725
| | | | llvm-svn: 182125
* R600: Rename 128 bit registers.Vincent Lejeune2013-05-172-10/+9
| | | | | | | | | Almost all instructions that takes a 128 bits reg as input (fetch, export...) have the abilities to swizzle their argument and output. Instead of printing default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions print potentially optimized swizzles themselves. llvm-svn: 182124
* R600: Some factorizationVincent Lejeune2013-05-175-203/+221
| | | | llvm-svn: 182123
* R600: Factorize Fetch size limit inside AMDGPUSubTargetVincent Lejeune2013-05-174-13/+13
| | | | llvm-svn: 182122
* R600: prettier dump of clampVincent Lejeune2013-05-172-4/+4
| | | | llvm-svn: 182121
* R600: Fix encoding for R600 family GPUsTom Stellard2013-05-171-0/+7
| | | | | | | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64193 https://bugs.freedesktop.org/show_bug.cgi?id=64257 https://bugs.freedesktop.org/show_bug.cgi?id=64320 NOTE: This is a candidate for the 3.3 branch. llvm-svn: 182113
* R600: Pass MCSubtargetInfo reference to R600CodeEmitterTom Stellard2013-05-173-6/+10
| | | | llvm-svn: 182112
* R600/SI: return undef instead of null for skipped argumentsChristian Konig2013-05-171-2/+2
| | | | | | | | | | | This is a candidate for the stable branch. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=64694 Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182084
* R600/SI: Add processor type for Hainan asicTom Stellard2013-05-142-1/+3
| | | | | | | | | | Patch by: Alex Deucher Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181792
* Remove unused fields and arguments.Rafael Espindola2013-05-133-13/+6
| | | | llvm-svn: 181706
* Remove the MachineMove class.Rafael Espindola2013-05-131-0/+1
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. llvm-svn: 181680
* Fix the R600 build.Rafael Espindola2013-05-102-3/+2
| | | | llvm-svn: 181621
* R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen ↵Tom Stellard2013-05-105-1217/+12
| | | | | | | | | | | | | | patterns The BFE optimization was the only one we were actually using, and it was emitting an intrinsic that we don't support. https://bugs.freedesktop.org/show_bug.cgi?id=64201 Reviewed-by: Christian König <christian.koenig@amd.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181580
* R600: Expand SUB for v2i32/v4i32Tom Stellard2013-05-101-0/+2
| | | | | | | | | | Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181579
* R600: Expand MUL for v4i32/v2i32Tom Stellard2013-05-101-0/+2
| | | | | | | | | | | | Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181578
* R600: Expand SRA for v4i32/v2i32Tom Stellard2013-05-101-0/+2
| | | | | | | | | | | | v2: Add v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181577
* R600: Expand vselect for v4i32 and v2i32Tom Stellard2013-05-101-0/+3
| | | | | | | | | | | | v2: Add vselect v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181576
* R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcodeTom Stellard2013-05-062-1/+14
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181269
* R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemaskTom Stellard2013-05-061-1/+1
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181268
* R600/SI: Add intrinsic for texture image loadingTom Stellard2013-05-063-10/+46
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181267
* R600/SI: Add pattern for uint_to_fpTom Stellard2013-05-061-1/+3
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181266
* R600/SI: Add patterns for integer maxima / minimaTom Stellard2013-05-061-4/+12
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181265
* R600/SI: Add pattern for AMDGPU.trunc intrinsicTom Stellard2013-05-061-1/+3
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181263
* R600: Remove dead code from the CodeEmitter v2Tom Stellard2013-05-063-400/+64
| | | | | | | | | v2: - Replace switch statement with TSFlags query Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181229
* R600: Emit config values in register / value pairsTom Stellard2013-05-062-3/+55
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181228
* R600: Stop emitting the instruction type byte before each instructionTom Stellard2013-05-061-33/+2
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181225
* R600: Emit ISA for CALL_FS_* instructionsTom Stellard2013-05-061-1/+0
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181223
* R600: Expand vector or, shl, srl, and xor nodesTom Stellard2013-05-031-0/+8
| | | | llvm-svn: 181035
* R600: BFI_INT is a vector-only instructionTom Stellard2013-05-031-1/+1
| | | | llvm-svn: 181034
* R600: Add pattern for SHA-256 Ma functionTom Stellard2013-05-033-0/+17
| | | | | | This can be optimized using the BFI_INT instruction. llvm-svn: 181033
* R600: Clean up comments in Processors.tdTom Stellard2013-05-031-5/+1
| | | | llvm-svn: 181032
* R600: Signed literals are 64bits wideVincent Lejeune2013-05-021-3/+3
| | | | llvm-svn: 180960
* R600: If previous bundle is dot4, PV valid chan is always XVincent Lejeune2013-05-021-38/+51
| | | | llvm-svn: 180959
* R600: Improve asmPrint of ALU clauseVincent Lejeune2013-05-023-4/+20
| | | | llvm-svn: 180957
* R600: Prettier asmPrint of AluVincent Lejeune2013-05-024-13/+45
| | | | llvm-svn: 180956
* R600: Use new tablegen syntax for patternsTom Stellard2013-05-023-447/+381
| | | | | | | | All but two patterns have been converted to the new syntax. The remaining two patterns will require COPY_TO_REGCLASS instructions, which the VLIW DAG Scheduler cannot handle. llvm-svn: 180922
* R600/SI: remove nonsense select patternTom Stellard2013-05-021-8/+1
| | | | | | | | Fortunately this pattern never matched, otherwise we would have generated incorrect code. Signed-off-by: Christian K??nig <christian.koenig@amd.com> llvm-svn: 180921
* R600: Always use texture cache for compute shadersVincent Lejeune2013-04-301-2/+6
| | | | | | This will improve the performance of memory reads. llvm-svn: 180762
* R600: use native for aluVincent Lejeune2013-04-304-4/+135
| | | | llvm-svn: 180761
* R600: Packetize instructionsVincent Lejeune2013-04-306-3/+464
| | | | llvm-svn: 180760
* R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chipsVincent Lejeune2013-04-305-32/+105
| | | | llvm-svn: 180759
* R600: Add a Bank Swizzle operandVincent Lejeune2013-04-304-11/+19
| | | | llvm-svn: 180758
* R600: Take inner dependency into tex/vtx clausesVincent Lejeune2013-04-301-0/+34
| | | | llvm-svn: 180757
* R600: Turn TEX/VTX into native instructionsVincent Lejeune2013-04-303-15/+50
| | | | llvm-svn: 180756
* R600: Add FetchInst bit to instruction defs to denote vertex/tex instructionsVincent Lejeune2013-04-309-58/+95
| | | | | | v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache llvm-svn: 180755
* R600: Add some new processor variantsVincent Lejeune2013-04-302-1/+3
| | | | llvm-svn: 180753
* R600: Clean up instruction class definitionsVincent Lejeune2013-04-301-23/+14
| | | | llvm-svn: 180752
* R600: config section now reports use of killgtVincent Lejeune2013-04-301-0/+4
| | | | llvm-svn: 180751
OpenPOWER on IntegriCloud