| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | R600: Make sure to schedule AR register uses and defs in the same clause | Tom Stellard | 2013-06-05 | 3 | -4/+40 | |
| | | | | | | Reviewed-by: vljn at ovi.com llvm-svn: 183294 | |||||
| * | Revert "R600: Add a pass that merge Vector Register" | Rafael Espindola | 2013-06-05 | 4 | -370/+0 | |
| | | | | | | | This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing. llvm-svn: 183286 | |||||
| * | R600: Add a pass that merge Vector Register | Vincent Lejeune | 2013-06-04 | 4 | -0/+370 | |
| | | | | | llvm-svn: 183279 | |||||
| * | R600: Const/Neg/Abs can be folded to dot4 | Vincent Lejeune | 2013-06-04 | 5 | -47/+186 | |
| | | | | | llvm-svn: 183278 | |||||
| * | R600: Swizzle texture/export instructions | Vincent Lejeune | 2013-06-04 | 2 | -20/+126 | |
| | | | | | llvm-svn: 183229 | |||||
| * | Silencing an MSVC warning about mixing bool and unsigned int. | Aaron Ballman | 2013-06-04 | 1 | -1/+1 | |
| | | | | | llvm-svn: 183176 | |||||
| * | R600/SI: Add support for work item and work group intrinsics | Tom Stellard | 2013-06-03 | 3 | -15/+88 | |
| | | | | | llvm-svn: 183138 | |||||
| * | R600/SI: Add a calling convention for compute shaders | Tom Stellard | 2013-06-03 | 3 | -9/+39 | |
| | | | | | llvm-svn: 183137 | |||||
| * | R600/SI: Custom lower i64 sign_extend | Tom Stellard | 2013-06-03 | 2 | -0/+19 | |
| | | | | | llvm-svn: 183136 | |||||
| * | R600/SI: Adjust some instructions' out register class after ISel | Tom Stellard | 2013-06-03 | 2 | -0/+52 | |
| | | | | | | | | This is necessary to avoid generating VGPR to SGPR copies in some cases. llvm-svn: 183135 | |||||
| * | R600/SI: Handle REG_SEQUENCE in fitsRegClass() | Tom Stellard | 2013-06-03 | 1 | -3/+13 | |
| | | | | | llvm-svn: 183134 | |||||
| * | R600/SI: Handle nodes with glue results correctly ↵ | Tom Stellard | 2013-06-03 | 1 | -0/+16 | |
| | | | | | | | SITargetLowering::foldOperands() llvm-svn: 183133 | |||||
| * | R600/SI: Fixup CopyToReg register class in PostprocessISelDAG() | Tom Stellard | 2013-06-03 | 1 | -5/+33 | |
| | | | | | | | | | | | The CopyToReg nodes will sometimes try to copy a value from a VGPR to an SGPR. This kind of copy is not possible, so we need to detect VGPR->SGPR copies and do something else. The current strategy is to replace these copies with VGPR->VGPR copies and hope that all the users of CopyToReg can accept VGPRs as arguments. llvm-svn: 183132 | |||||
| * | R600/SI: Add support for global loads | Tom Stellard | 2013-06-03 | 3 | -4/+39 | |
| | | | | | llvm-svn: 183131 | |||||
| * | R600/SI: Rework MUBUF store instructions | Tom Stellard | 2013-06-03 | 5 | -42/+71 | |
| | | | | | | | | The lowering of stores is now mostly handled in the tablegen files. No more BUFFER_STORE nodes I generated during legalization. llvm-svn: 183130 | |||||
| * | R600: 3 op instructions have no write bit but the result are store in PV | Vincent Lejeune | 2013-06-03 | 1 | -3/+1 | |
| | | | | | llvm-svn: 183111 | |||||
| * | R600: CALL_FS consumes a stack size entry | Vincent Lejeune | 2013-06-03 | 1 | -0/+1 | |
| | | | | | llvm-svn: 183108 | |||||
| * | R600: use capital letter for PV channel | Vincent Lejeune | 2013-06-03 | 1 | -4/+4 | |
| | | | | | llvm-svn: 183107 | |||||
| * | R600: Constraints input regs of interp_xy,_zw | Vincent Lejeune | 2013-06-03 | 2 | -11/+15 | |
| | | | | | llvm-svn: 183106 | |||||
| * | Make SubRegIndex size mandatory, following r183020. | Ahmed Bougacha | 2013-05-31 | 1 | -1/+2 | |
| | | | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. llvm-svn: 183061 | |||||
| * | Temporary fix to get rid of gcc warning. | Patrik Hagglund | 2013-05-29 | 1 | -1/+10 | |
| | | | | | llvm-svn: 182832 | |||||
| * | Track IR ordering of SelectionDAG nodes 2/4. | Andrew Trick | 2013-05-25 | 8 | -45/+44 | |
| | | | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703 | |||||
| * | R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg | Tom Stellard | 2013-05-23 | 1 | -2/+9 | |
| | | | | | | | | | | Patch by: Vincent Lejeune https://bugs.freedesktop.org/show_bug.cgi?id=64877 NOTE: This is a candidate for the 3.3 branch. llvm-svn: 182600 | |||||
| * | Move passes from namespace llvm into anonymous namespaces. Sort includes ↵ | Benjamin Kramer | 2013-05-23 | 14 | -35/+35 | |
| | | | | | | | while there. llvm-svn: 182594 | |||||
| * | R600: Hide symbols of implementation details. | Benjamin Kramer | 2013-05-23 | 4 | -63/+25 | |
| | | | | | | | Also removes an unused function. llvm-svn: 182587 | |||||
| * | Setting the default value (fixes CRT assertions about uninitialized variable ↵ | Aaron Ballman | 2013-05-23 | 1 | -3/+3 | |
| | | | | | | | use when doing debug MSVC builds), and fixing coding style. llvm-svn: 182585 | |||||
| * | Fix 32 bit build in c++11 mode. | Rafael Espindola | 2013-05-23 | 1 | -1/+1 | |
| | | | | | | | | | The error was: error: non-constant-expression cannot be narrowed from type 'long long' to 'long' in initializer list [-Wc++11-narrowing] MI.getOperand(6).getImm() & 0x1F, llvm-svn: 182584 | |||||
| * | Fix a leak on the r600 backend. | Rafael Espindola | 2013-05-23 | 2 | -8/+12 | |
| | | | | | | | This should bring the valgrind bot back to life. llvm-svn: 182561 | |||||
| * | clang-format this file. | Rafael Espindola | 2013-05-23 | 1 | -29/+25 | |
| | | | | | llvm-svn: 182560 | |||||
| * | Fix use after free (pr16103). | Rafael Espindola | 2013-05-22 | 1 | -7/+22 | |
| | | | | | llvm-svn: 182482 | |||||
| * | Check that a function starts with llvm. before using GET_FUNCTION_RECOGNIZER. | Rafael Espindola | 2013-05-22 | 1 | -0/+3 | |
| | | | | | | | Fixes a use of uninitialized memory found by asan and valgind. llvm-svn: 182480 | |||||
| * | R600ISelLowering.cpp: Avoid "using namespace Intrinsic;" to appease MSC. ↵ | NAKAMURA Takumi | 2013-05-22 | 1 | -18/+15 | |
| | | | | | | | | | Specify namespaces explicitly here. MSC is confused about "memcpy" between <cstring> and llvm::Intrinsic::memcpy, when llvm::Intrinsic were exposed. llvm-svn: 182452 | |||||
| * | R600: Whitespace and untabify. | NAKAMURA Takumi | 2013-05-22 | 1 | -2/+2 | |
| | | | | | llvm-svn: 182451 | |||||
| * | Create an FPOW SDNode opcode def in the target independent .td file rather ↵ | Owen Anderson | 2013-05-22 | 1 | -2/+0 | |
| | | | | | | | than in a specific backend. llvm-svn: 182450 | |||||
| * | Attempt to fix the mingw32 bot. | Rafael Espindola | 2013-05-22 | 1 | -4/+4 | |
| | | | | | | | | This should hopefully fix http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32 llvm-svn: 182446 | |||||
| * | s/u_int32_t/uint32_t/ | Rafael Espindola | 2013-05-22 | 1 | -2/+2 | |
| | | | | | llvm-svn: 182444 | |||||
| * | Fix warning in non-assert build. | Rafael Espindola | 2013-05-22 | 1 | -0/+2 | |
| | | | | | llvm-svn: 182443 | |||||
| * | R600: Fix bug detected by GCC warning. | Benjamin Kramer | 2013-05-20 | 1 | -2/+2 | |
| | | | | | | | | | | R600TextureIntrinsicsReplacer.cpp:232: warning: the address of ‘ArgsType’ will always evaluate as ‘true’ This doesn't have any effect on the output as a vararg intrinsic behaves the same way as a non-vararg one. llvm-svn: 182293 | |||||
| * | R600/SI: Use a multiclass for MUBUF_Load_Helper | Tom Stellard | 2013-05-20 | 2 | -20/+30 | |
| | | | | | | | | This will simplify the instructions and also the pattern definitions. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182288 | |||||
| * | R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions | Tom Stellard | 2013-05-20 | 1 | -0/+1 | |
| | | | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182287 | |||||
| * | R600/SI: Add pattern for rotr | Tom Stellard | 2013-05-20 | 1 | -0/+2 | |
| | | | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182286 | |||||
| * | R600: Swap the legality of rotl and rotr | Tom Stellard | 2013-05-20 | 7 | -28/+11 | |
| | | | | | | | The hardware supports rotr and not rotl. llvm-svn: 182285 | |||||
| * | R600/SI: Add patterns for 64-bit shift operations | Tom Stellard | 2013-05-20 | 2 | -3/+22 | |
| | | | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182284 | |||||
| * | R600/SI: Use the same names for VOP3 operands and encoding fields | Tom Stellard | 2013-05-20 | 2 | -37/+37 | |
| | | | | | | | | | This makes it possible to reorder the operands without breaking the encoding. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182283 | |||||
| * | R600/SI: Make fitsRegClass() operands const | Tom Stellard | 2013-05-20 | 2 | -2/+3 | |
| | | | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182282 | |||||
| * | Add LLVMContext argument to getSetCCResultType | Matt Arsenault | 2013-05-18 | 4 | -11/+11 | |
| | | | | | llvm-svn: 182180 | |||||
| * | Fix the build in c++11 mode. | Rafael Espindola | 2013-05-17 | 1 | -2/+2 | |
| | | | | | | | | | | | | | The errors were: non-constant-expression cannot be narrowed from type 'int64_t' (aka 'long') to 'uint32_t' (aka 'unsigned int') in initializer list and non-constant-expression cannot be narrowed from type 'long' to 'uint32_t' (aka 'unsigned int') in initializer list llvm-svn: 182168 | |||||
| * | R600: Lower int_load_input to copyFromReg instead of Register node | Vincent Lejeune | 2013-05-17 | 1 | -1/+5 | |
| | | | | | | | | It solves a bug uncovered by dot4 patch where the register class of int_load_input use was ignored. llvm-svn: 182130 | |||||
| * | R600: Use bottom up scheduling algorithm | Vincent Lejeune | 2013-05-17 | 4 | -25/+37 | |
| | | | | | llvm-svn: 182129 | |||||
| * | R600: Use depth first scheduling algorithm | Vincent Lejeune | 2013-05-17 | 2 | -79/+31 | |
| | | | | | | | | It should increase PV substitution opportunities and lower gpr usage (pending computations path are "flushed" sooner) llvm-svn: 182128 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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