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* R600: Use the same compute kernel calling convention for all GPUsTom Stellard2013-07-233-11/+27
| | | | | | | | A side-effect of this is that now the compiler expects kernel arguments to be 4-byte aligned. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186916
* R600: Use correct LoadExtType when lowering kernel argumentsTom Stellard2013-07-231-1/+9
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186915
* R600: Clean up extended load patternsTom Stellard2013-07-234-15/+31
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186914
* R600: Expand vector FNEGTom Stellard2013-07-231-0/+3
| | | | llvm-svn: 186913
* R600: Don't emit empty then clause and use alu_pop_afterVincent Lejeune2013-07-193-11/+46
| | | | llvm-svn: 186725
* R600: Simplify AMDILCFGStructurize by removing templates and assuming single ↵Vincent Lejeune2013-07-193-2494/+1324
| | | | | | exit llvm-svn: 186724
* R600: Replace legacy debug code in AMDILCFGStructurizer.cppVincent Lejeune2013-07-191-228/+235
| | | | llvm-svn: 186723
* R600/SI: Fix crash with VSELECTTom Stellard2013-07-182-1/+13
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=66175 llvm-svn: 186616
* R600/SI: Add support for v2f32 loadsTom Stellard2013-07-183-1/+5
| | | | llvm-svn: 186615
* R600/SI: Add support for v2f32 storesTom Stellard2013-07-182-0/+6
| | | | llvm-svn: 186614
* R600: Expand VSELECT for all typesTom Stellard2013-07-182-3/+3
| | | | llvm-svn: 186613
* Move string pointer from being a static class member to just a static global ↵Craig Topper2013-07-172-7/+2
| | | | | | in the one file its needed in. llvm-svn: 186476
* Add 'const' qualifiers to static const char* variables.Craig Topper2013-07-161-7/+7
| | | | llvm-svn: 186371
* R600/SI: Add support for 64-bit loadsTom Stellard2013-07-153-1/+29
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=65873 llvm-svn: 186339
* Make some arrays 'static const'Craig Topper2013-07-154-11/+11
| | | | llvm-svn: 186307
* Use llvm::array_lengthof to replace sizeof(array)/sizeof(array[0]).Craig Topper2013-07-152-5/+5
| | | | llvm-svn: 186301
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-143-6/+6
| | | | | | size. llvm-svn: 186274
* R600: Remove unsafe type punning. No intended functionality change.Benjamin Kramer2013-07-121-6/+4
| | | | llvm-svn: 186196
* R600/SI: Add support for f64 kernel argumentsTom Stellard2013-07-121-1/+1
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186182
* R600/SI: Implement select and compares for SITom Stellard2013-07-121-6/+18
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186181
* R600/SI: Add fsqrt pattern for SITom Stellard2013-07-121-2/+6
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186180
* R600/SI: Add double precision fsub pattern for SITom Stellard2013-07-122-3/+29
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186179
* R600/SI: SI support for 64bit ConstantFPTom Stellard2013-07-122-0/+19
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186178
* R600/SI: Add initial double precision support for SITom Stellard2013-07-123-1/+36
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186177
* Replacing an empty switch with its moral equivalent. No functional changes ↵Aaron Ballman2013-07-101-3/+1
| | | | | | intended. llvm-svn: 186017
* R600/SI: Initial local memory supportMichel Danzer2013-07-106-3/+34
| | | | | | | Enough for the radeonsi driver to use it for calculating derivatives. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186012
* R600/SI: Add pattern for the AMDGPU.barrier.local intrinsicMichel Danzer2013-07-101-1/+10
| | | | | | | lit test coverage to follow in the next commit. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186011
* R600/SI: Add intrinsic for retrieving the current thread IDMichel Danzer2013-07-102-2/+9
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186010
* R600/SI: Initial support for LDS/GDS instructionsMichel Danzer2013-07-105-0/+68
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186009
* R600/SI: Add intrinsics for texture sampling with user derivativesMichel Danzer2013-07-102-1/+7
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186008
* R600: Do not predicated basic block with multiple alu clauseVincent Lejeune2013-07-096-7/+64
| | | | | | | | | Test is not included as it is several 1000 lines long. To test this functionnality, a test case must generate at least 2 ALU clauses, where an ALU clause is ~110 instructions long. NOTE: This is a candidate for the stable branch. llvm-svn: 185943
* R600: Fix a rare bug where swizzle optimization returns wrong valuesVincent Lejeune2013-07-091-2/+3
| | | | llvm-svn: 185942
* R600: Fix wrong export reswizzlingVincent Lejeune2013-07-091-4/+0
| | | | llvm-svn: 185941
* R600: Use DAG lowering pass to handle fcos/fsinVincent Lejeune2013-07-094-23/+52
| | | | | NOTE: This is a candidate for the stable branch. llvm-svn: 185940
* R600: Print Export SwizzleVincent Lejeune2013-07-091-2/+2
| | | | llvm-svn: 185939
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-031-12/+12
| | | | | | specifying the vector size. llvm-svn: 185540
* Remove address spaces from MC.Rafael Espindola2013-07-022-6/+0
| | | | | | | | This is dead code since PIC16 was removed in 2010. The result was an odd mix, where some parts would carefully pass it along and others would assert it was zero (most of the object streamer for example). llvm-svn: 185436
* Add a newline.Chad Rosier2013-07-011-1/+1
| | | | llvm-svn: 185385
* R600: Fix an unitialized variable in R600InstrInfo.cppVincent Lejeune2013-06-301-1/+1
| | | | llvm-svn: 185294
* R600: Unbreak GCC build.Benjamin Kramer2013-06-291-1/+2
| | | | | | | operator++ on an enum is not legal. clang happens to accept it anyways, I think that's a known bug. llvm-svn: 185269
* R600: Support schedule and packetization of trans-only instVincent Lejeune2013-06-297-90/+246
| | | | llvm-svn: 185268
* R600: Bank Swizzle now display SCL equivalentVincent Lejeune2013-06-293-12/+12
| | | | llvm-svn: 185267
* R600/SI: Add processor types for each CIK variantTom Stellard2013-06-281-0/+3
| | | | | | | | Patch By: Alex Deucher Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> llvm-svn: 185209
* R600: Add local memory support via LDSTom Stellard2013-06-2817-24/+254
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185162
* R600: Add support for GROUP_BARRIER instructionTom Stellard2013-06-287-3/+64
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185161
* R600: Add ALUInst bit to tablegen definitions v2Tom Stellard2013-06-284-4/+8
| | | | | | | | v2: - Remove functions left over from a previous rebase. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185160
* R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard2013-06-2510-228/+160
| | | | llvm-svn: 184880
* R600: Consolidate expansion of v2i32/v4i32 ops for EG/SIAaron Watry2013-06-253-49/+22
| | | | | | | | | | By default, we expand these operations for both EG and SI. Move the duplicated code into a common space for now. If the targets ever actually implement these operations as instructions, we can override that in the relevant target. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184848
* R600/SI: Expand xor v2i32/v4i32Aaron Watry2013-06-251-0/+3
| | | | | | | Add test cases for both vector sizes on SI and also add v2i32 test for EG. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184846
* R600/SI: Expand urem of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
| | | | | | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Note: I followed the guidance of the v4i32 EG check... UREM produces really complex code, so let's just check that the instruction was lowered successfully. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184844
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