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* R600: Workaround for cayman loop bugVincent Lejeune2013-12-022-0/+14
| | | | llvm-svn: 196121
* Change the default of AsmWriterClassName and isMCAsmWriter.Rafael Espindola2013-12-021-10/+0
| | | | llvm-svn: 196065
* [CMake] Let add_public_tablegen_target() provide intrinsics_gen, too.NAKAMURA Takumi2013-11-282-4/+0
| | | | | | | | | | I think, in principle, intrinsics_gen may be added explicitly. That said, it can be added incidentally, since each target already has dependencies to llvm-tblgen. Almost all source files depend on both CommonTaleGen and intrinsics_gen. Explicit add_dependencies() have been pruned under lib/Target. llvm-svn: 195929
* [CMake] Let add_public_tablegen_target responsible to provide dependency to ↵NAKAMURA Takumi2013-11-284-6/+2
| | | | | | | | | CommonTableGen. add_public_tablegen_target adds *CommonTableGen to LLVM_COMMON_DEPENDS. LLVM_COMMON_DEPENDS affects add_llvm_library (and other add_target stuff) within its scope. llvm-svn: 195927
* [CMake] Prune include_directories() in llvm/lib/Target, take #2.NAKAMURA Takumi2013-11-282-4/+0
| | | | | | I forgot to commit them. They were staging in my local repo. llvm-svn: 195924
* The R600 has its own asm printer which doesn't use GlobalPrefix. Drop it.Rafael Espindola2013-11-271-1/+0
| | | | llvm-svn: 195883
* R600: Expand vector FABSTom Stellard2013-11-271-0/+1
| | | | | NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195881
* R600/SI: Implement spilling of SGPRs v5Tom Stellard2013-11-276-13/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions. v2: - Fix encoding of Lane Mask - Use correct register flags, so we don't overwrite the low dword when restoring multi-dword registers. v3: - Register spilling seems to hang the GPU, so replace all shaders that need spilling with a dummy shader. v4: - Fix *LANE definitions - Change destination reg class for 32-bit SMRD instructions v5: - Remove small optimization that was crashing Serious Sam 3. https://bugs.freedesktop.org/show_bug.cgi?id=68224 https://bugs.freedesktop.org/show_bug.cgi?id=71285 NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195880
* R600/SI: Use SGPR_32 register class for 32-bit SMRD outputsTom Stellard2013-11-271-2/+5
| | | | | | | | Writing to the M0 register from an SMRD instruction hangs the GPU, so we need to use the SGPR_32 register class, which does not include M0. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195879
* R600: Add support for ISD::FROUNDTom Stellard2013-11-273-4/+18
| | | | | NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195878
* R600/SI: Fixing handling of condition codesTom Stellard2013-11-224-76/+98
| | | | | | | | We were ignoring the ordered/onordered bits and also the signed/unsigned bits of condition codes when lowering the DAG to MachineInstrs. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195514
* R600: Implement TargetInstrInfo::isLegalToSplitMBBAt()Tom Stellard2013-11-222-0/+14
| | | | | | | | | | | | Splitting a basic block will create a new ALU clause, so we need to make sure we aren't moving uses of registers that are local to their current clause into a new one. I had a test case for this, but unfortunately unrelated schedule changes invalidated it, and I wasn't been able to come up with another one. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195399
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-1912-4/+44
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
* R600/SI: Fix moveToVALU when the first operand is VSrc.Matt Arsenault2013-11-182-2/+4
| | | | | | | Moving into a VSrc doesn't always work, since it could be replaced with an SGPR later. llvm-svn: 195042
* R600/SI: Fix multiple SGPR reads when using VCC.Matt Arsenault2013-11-181-0/+18
| | | | | | | No other SGPR operands are allowed, so if VCC is used, move the other to a VGPR. llvm-svn: 195041
* R600/SI: Implement add i64, but do not yet enable.Matt Arsenault2013-11-182-0/+29
| | | | | | | | Test doesn't actually check the output. I need to fix add i64 being matched for the addressing calculations. llvm-svn: 195040
* R600/SI: Specify SSrc operandsMatt Arsenault2013-11-181-2/+2
| | | | llvm-svn: 195039
* R600/SI: addc / adde i32 are legalMatt Arsenault2013-11-181-0/+2
| | | | llvm-svn: 195038
* R600/SI: Match addc to S_ADD_U32.Matt Arsenault2013-11-181-0/+7
| | | | | | The carry always goes to SCC. llvm-svn: 195037
* R600/SI: Match adde/sube to S_ADDC_U32/S_SUBB_U32Matt Arsenault2013-11-181-2/+4
| | | | llvm-svn: 195036
* R600/SI: Specify S_ADD/S_SUB set SCC and add is commutableMatt Arsenault2013-11-181-1/+13
| | | | llvm-svn: 195035
* R600/SI: Move patterns to match add / sub to scalar instructionsMatt Arsenault2013-11-182-10/+16
| | | | llvm-svn: 195034
* R600/SI: Fix extra defs of VCC / SCC.Matt Arsenault2013-11-181-4/+15
| | | | | | | When replacing scalar operations with vector, the wrong implicit output register was used. llvm-svn: 195033
* R600: Enable the IR structurizer by defaultTom Stellard2013-11-183-6/+5
| | | | llvm-svn: 195031
* R600: Fix a crash in the AMDILCFGStrucurizerTom Stellard2013-11-181-6/+7
| | | | | | | The ifPatternMatch() function was not correctly reporting the number of matches in some cases. llvm-svn: 195030
* R600: Add a SubtargetFeatture for disabling the ifcvt pass.Tom Stellard2013-11-184-1/+14
| | | | | | This is useful when writing test cases for the AMDIL structurizer. llvm-svn: 195029
* R600: Use lower-case for EnableIRStructurizer featureTom Stellard2013-11-181-1/+1
| | | | | | | llc converts all values passed to -mattr= to lowercase, so this enables us to toggle this feature when using llc. llvm-svn: 195028
* R600/SI: Fix illegal VGPR->SGPR copy inside of loopTom Stellard2013-11-181-2/+1
| | | | llvm-svn: 195026
* R600/SI: Fix another case of illegal VGPR->SGPR copyTom Stellard2013-11-181-3/+2
| | | | llvm-svn: 195025
* Revert r194865 and r194874.Alexey Samsonov2013-11-1812-44/+4
| | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. llvm-svn: 194997
* R600: Make dot_4 instructions predicableVincent Lejeune2013-11-161-0/+19
| | | | llvm-svn: 194927
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-1512-4/+44
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
* Make method staticMatt Arsenault2013-11-152-2/+2
| | | | llvm-svn: 194858
* R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()Tom Stellard2013-11-151-0/+1
| | | | | | This fixes a crash with GNOME settings manager. llvm-svn: 194836
* Add target hook to prevent folding some bitcasted loads.Matt Arsenault2013-11-152-0/+13
| | | | | | | | | | | | | This is to avoid this transformation in some cases: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently casting the load to a smaller vector of larger types and loading is more efficient. Patch by Micah Villmow. llvm-svn: 194783
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-159-51/+116
| | | | | | | | | | | | | | | | | | | | | | | | The LDS output queue is accessed via the OQAP register. The OQAP register cannot be live across clauses, so if value is written to the output queue, it must be retrieved before the end of the clause. With the machine scheduler, we cannot statisfy this constraint, because it lacks proper alias analysis and it will mark some LDS accesses as having a chain dependency on vertex fetches. Since vertex fetches require a new clauses, the dependency may end up spiltting OQAP uses and defs so the end up in different clauses. See the lds-output-queue.ll test for a more detailed explanation. To work around this issue, we now combine the LDS read and the OQAP copy into one instruction and expand it after register allocation. This patch also adds some checks to the EmitClauseMarker pass, so that it doesn't end a clause with a value still in the output queue and removes AR.X and OQAP handling from the scheduler (AR.X uses and defs were already being expanded post-RA, so the scheduler will never see them). Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 194755
* R600/SI: Add processor type for HawaiiTom Stellard2013-11-141-0/+1
| | | | | | | | Patch by: Alex Deucher Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> llvm-svn: 194752
* R600/SI: Remove redundant legalizeOperands callMatt Arsenault2013-11-141-1/+0
| | | | llvm-svn: 194749
* Add #include raw_ostream.h in lib/Target/R600/SIFixSGPRCopies.cppHans Wennborg2013-11-141-0/+1
| | | | | | This was casuing my release+asserts build on Windows to fail. llvm-svn: 194747
* R600/SI: Specify S_ADDK/S_MULK set SCC and are commutableMatt Arsenault2013-11-141-2/+5
| | | | llvm-svn: 194738
* Indentation fixesMatt Arsenault2013-11-142-3/+2
| | | | llvm-svn: 194688
* Add a commentMatt Arsenault2013-11-141-1/+3
| | | | llvm-svn: 194684
* Fix trailing whitespace in debug printingMatt Arsenault2013-11-141-1/+1
| | | | llvm-svn: 194683
* R600/SIFixSGPRCopies.cpp: Fix \param to \return. [-Wdocumentation]NAKAMURA Takumi2013-11-141-1/+1
| | | | llvm-svn: 194662
* Whitespace.NAKAMURA Takumi2013-11-141-4/+4
| | | | llvm-svn: 194661
* R600: Fix uninitialized variable usageTom Stellard2013-11-131-5/+5
| | | | llvm-svn: 194632
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-1324-134/+402
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-139-35/+528
| | | | | | | | | | | | | | All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. llvm-svn: 194625
* Remove AllowQuotesInName and friends from MCAsmInfo.Rafael Espindola2013-11-131-3/+0
| | | | | | | | | | | Accepting quotes is a property of an assembler, not of an object file. For example, ELF can support any names for sections and symbols, but the gnu assembler only accepts quotes in some contexts and llvm-mc in a few more. LLVM should not produce different symbols based on a guess about which assembler will be reading the code it is printing. llvm-svn: 194575
* R600: Fix selection failure on EXTLOADMatt Arsenault2013-11-131-1/+9
| | | | llvm-svn: 194547
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