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* R600: Add AR_X to the R600_TReg_X register class.Tom Stellard2013-02-191-1/+1
| | | | | NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175519
* R600: Mark all members of the TRegMem register class as reservedTom Stellard2013-02-191-0/+6
| | | | | | | | This stops the Machine Verifier from complaining about uses of undefined physical registers. NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175518
* R600: Fix scheduler crash caused by invalid MachinePointerInfoTom Stellard2013-02-191-1/+1
| | | | | | | | | | | | | | Kernel function arguments are lowered to loads from the PARAM_I address space. When creating these load instructions, we were initializing their MachinePointerInfo with an Arguement object that was not attached to any function. This was causing the MachineScheduler to crash when it tried to access the parent of the Arguement. This has been fixed by initializing the MachinePointerInfo with a UndefValue instead. NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175517
* R600: Fix tracking of implicit defs in the IndirectAddressing passTom Stellard2013-02-191-7/+25
| | | | | | | | | In some cases, we were losing track of live implicit registers which was creating dead defs and causing the scheduler to produce invalid code. NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175516
* Use LLVM_DELETED_FUNCTION rather than '// do not implement' comments.David Blaikie2013-02-182-4/+4
| | | | | | | Also removes some redundant DNI comments on function declarations already using the macro. llvm-svn: 175466
* R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad patternVincent Lejeune2013-02-187-23/+15
| | | | llvm-svn: 175446
* R600: Support for TBOVincent Lejeune2013-02-183-1/+58
| | | | | | | NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175445
* R600: Increase number of ArrayBase Reg to 32Vincent Lejeune2013-02-181-2/+2
| | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175443
* Target/R600/CMakeLists.txt: Prune SILowerLiteralConstants.cpp corresponding ↵NAKAMURA Takumi2013-02-161-1/+0
| | | | | | to r175354. llvm-svn: 175361
* R600/SI: Add pattern to simplify i64 loadingChristian Konig2013-02-162-0/+9
| | | | | | | | This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175356
* R600/SI: nuke SReg_1 v3Christian Konig2013-02-167-118/+23
| | | | | | | | | | | | | | | | | It's completely unnecessary and can be replace with proper SReg_64 handling instead. This actually fixes a piglit test on SI. v2: use correct register class in addRegisterClass, set special classes as not allocatable v3: revert setting special classes as not allocateable This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175355
* R600/SI: cleanup literal handling v3Christian Konig2013-02-1610-195/+176
| | | | | | | | | | | | | | | | Seems to be allot simpler, and also paves the way for further improvements. v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW, use VGPR0 in dummy EXP, avoid compiler warning, break after encoding the first literal. v3: correctly use V_ADD_F32_e64 This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175354
* R600/SI: replace AllReg_* with [SV]Src_* v2Christian Konig2013-02-163-85/+89
| | | | | | | | | | | | Mark all the operands that can also have an immediate. v2: SOFFSET is also an SSrc_32 operand This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175353
* R600/SI: fix VOPC encoding v2Christian Konig2013-02-161-37/+16
| | | | | | | | | | | | | Previously it only worked because of coincident. v2: fix 64bit versions, use 0x80 (inline 0) instead of SGPR0 for the unused SRC2 This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175352
* R600/SI: move *_Helper definitions to SIInstrFormat.tdChristian Konig2013-02-162-66/+66
| | | | | | | | This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175351
* R600/SI: remove some more unused codeChristian Konig2013-02-162-52/+0
| | | | | | | | This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175350
* R600/structurizer: improve inverting conditionsChristian Konig2013-02-161-1/+39
| | | | | | | | | | Stop adding more instructions than necessary. This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175349
* R600/structurizer: improve loop handlingChristian Konig2013-02-161-196/+148
| | | | | | | | | | Generate more than one loop if it seems to make sense. This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175348
* R600/structurizer: improve finding condition valuesChristian Konig2013-02-161-9/+22
| | | | | | | | | | Using the new NearestCommonDominator class. This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175347
* R600/structurizer: improve PHI value findingChristian Konig2013-02-161-0/+6
| | | | | | | | | | Using the new NearestCommonDominator class. This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175346
* R600/structurizer: add class to find the Nearest Common DominatorChristian Konig2013-02-161-0/+66
| | | | | | | | This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175345
* R600/SI: Fix int_SI_fs_interp_constantMichel Danzer2013-02-145-37/+34
| | | | | | | | | | | | | | | | The important fix is that the constant interpolation value is stored in the parameter slot P0, which is encoded as 2. In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter slot as an operand to V_INTERP_MOV_F32 instead of hardcoding it there, and add a special operand class for the parameter slots for type checking and pretty printing. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175193
* R600: Do not fold single instruction with more that 3 kcache readVincent Lejeune2013-02-142-1/+3
| | | | | | | | | It fixes around 100 tfb piglit tests and 16 glean tests. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175183
* R600: Export instructions are no longer terminatorVincent Lejeune2013-02-141-2/+2
| | | | | | | | This allows MachineInstScheduler to reorder them, and thus make scheduling more efficient. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175182
* R600: Fold zero/one in export instructionsVincent Lejeune2013-02-143-80/+55
| | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175181
* R600: Do not fold modifier/litterals in vector instVincent Lejeune2013-02-141-2/+5
| | | | | | | | | This fixes a couple of regressions on (probably not just) cayman NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175180
* R600/SI: Check for empty stack in SIAnnotateControlFlow::isTopOfStackMichel Danzer2013-02-141-1/+1
| | | | | | | Fixes assertion failure in newly added lit test. Might just be a bandaid that needs to be revisited. llvm-svn: 175139
* R600: Add support for 128-bit parametersTom Stellard2013-02-132-0/+5
| | | | | NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175096
* R600: Fix regression with shadow array sampler on pre-SI GPUs.Michel Danzer2013-02-121-1/+1
| | | | | | | | | | | | | | | 'R600/SI: Use proper instructions for array/shadow samplers.' removed two cases from TEX_SHADOW. Vincent Lejeune reported on IRC that this broke some shadow array piglit tests with the r600g driver. Reinstating the removed cases should fix this, and still works with radeonsi as well. I will follow up with some lit tests which would have caught the regression. NOTE: This is a candidate for the Mesa stable branch. Tested-by: Vincent Lejeune <vljn@ovi.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174963
* R600/SI: Use V_ADD_F32 instead of V_MOV_B32 for clamp/neg/abs modifiers.Michel Danzer2013-02-111-15/+9
| | | | | | | | | | | | | The modifiers don't seem to have any effect with V_MOV_B32, supposedly it's meant to just move bits untouched. Fixes 46 piglit tests with radeonsi, though unfortunately 11 of those had just regressed because they started using the clamp modifier. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174890
* Test Commit - Remove some trailing whitespace in R600Instructions.tdVincent Lejeune2013-02-101-6/+6
| | | | llvm-svn: 174839
* R600: Dump the function name when TargetLowering::LowerCall() failsTom Stellard2013-02-081-0/+5
| | | | | | | Also output a more useful error message. NOTE: This is a candidate for the Mesa stable branch llvm-svn: 174763
* R600: rework flow creation in the structurizer v2Tom Stellard2013-02-081-177/+195
| | | | | | | | | | | | This fixes a couple of bugs and incorrect assumptions, in total four more piglit tests now pass. v2: fix small bug in the dominator updating Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 174762
* R600: fix loop analyses in the structurizerTom Stellard2013-02-081-113/+183
| | | | | | | | | | Patch by: Christian König Intersecting loop handling was wrong. Signed-off-by: Christian König <christian.koenig@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 174761
* R600: fix PHI value adding in the structurizerTom Stellard2013-02-081-65/+81
| | | | | | | | | | Otherwise we sometimes produce invalid code. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 174760
* R600/SI: cleanup VGPR encodingTom Stellard2013-02-075-178/+16
| | | | | | | | | | Remove all the unused code. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174656
* R600/SI: Handle VGPR64 destination in copyPhysReg().Tom Stellard2013-02-071-1/+9
| | | | | | | | | | Allows nexuiz to run with radeonsi. Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174655
* R600/SI: Add pattern for mul.Tom Stellard2013-02-071-0/+4
| | | | | | | | | | 20 more little piglits with radeonsi. Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174654
* R600/SI: simplify and fix SMRD encodingTom Stellard2013-02-076-154/+70
| | | | | | | | | | The _SGPR variants where wrong. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174653
* R600/SI: add proper 64bit immediate support v2Tom Stellard2013-02-073-12/+18
| | | | | | | | | | v2: rebased on current upstream Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174652
* R600: Add an explicit default processorTom Stellard2013-02-071-0/+1
| | | | | | | | | | | This is for the case when no processor is passed to the backend. This prevents the '' is not a recognized processor for this target (ignoring processor) warning from being generated by clang. llvm-svn: 174651
* R600/SI: Use proper instructions for array/shadow samplers.Tom Stellard2013-02-072-4/+54
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174634
* R600/SI: Make sample intrinsic address parameter type overloaded.Tom Stellard2013-02-073-22/+38
| | | | | | | | | | | | | Handle vectors of 1 to 16 integers. Change the intrinsic names to prevent the wrong one from being selected at runtime due to the overloading. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174633
* R600/SI: Add basic support for more integer vector types.Tom Stellard2013-02-075-11/+110
| | | | | | | | | | | | | v1i32, v2i32, v8i32 and v16i32. Only add VGPR register classes for integer vector types, to avoid attempts copying from VGPR to SGPR registers, which is not possible. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174632
* R600/SI: Add pattern for flog2Michel Danzer2013-02-071-1/+3
| | | | | | | 22 more little piglits with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174615
* R600: Consolidate sub register indices.Tom Stellard2013-02-078-93/+73
| | | | | | | | | | Use sub0-15 everywhere. Patch by: Michel Dänzerr Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 174610
* R600: Add support for SET*_DX10 instructionsTom Stellard2013-02-072-29/+131
| | | | | | | | | | | These instructions compare two floating point values and return an integer true (-1) or false (0) value. When compiling code generated by the Mesa GLSL frontend, the SET*_DX10 instructions save us four instructions for most branch decisions that use floating-point comparisons. llvm-svn: 174609
* R600: Fix assembly name for SETGT_INTTom Stellard2013-02-071-1/+1
| | | | llvm-svn: 174607
* R600: Support for indirect addressing v4Tom Stellard2013-02-0630-75/+1124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525
* Don't use MRI liveouts in R600.Jakob Stoklund Olesen2013-02-053-5/+14
| | | | | | | | | | | | Something very strange is going on with the output registers in this target. Its ISelLowering code is inserting dangling CopyToReg nodes, hoping that those physregs won't get clobbered before the RETURN. This patch adds the output registers as implicit uses on RETURN instructions in the custom emission pass. I'd much prefer to have those CopyToReg nodes glued to the RETURNs, but I don't see how. llvm-svn: 174400
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