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* R600/SI: Move SIInsertWaits into AMDGPUPassConfig::addPreSched2()Tom Stellard2014-12-031-1/+3
| | | | | | | This pass needs to be run after PrologEpilogInserter, because that pass may inserter spill code which reads or writes memory. llvm-svn: 223253
* R600/SI: Don't run SI passes on R600 subtargetsTom Stellard2014-12-031-1/+1
| | | | llvm-svn: 223252
* Silencing a 32-bit implicit conversion warning in MSVC; NFC.Aaron Ballman2014-12-031-1/+1
| | | | llvm-svn: 223237
* R600/SI: Fix SIFixSGPRCopies for copies to physical registersMatt Arsenault2014-12-031-1/+6
| | | | | | | This shows up when operands required to be passed in VCC are copied to. llvm-svn: 223208
* R600/SI: Remove incorrect assertionMatt Arsenault2014-12-031-5/+5
| | | | | | This can be a COPY to a physical register, such as VCC llvm-svn: 223207
* R600/SI: Remove i1 pseudo VALU opsMatt Arsenault2014-12-033-63/+70
| | | | | | | | | | | | | | Select i1 logical ops directly to 64-bit SALU instructions. Vector i1 values are always really in SGPRs, with each bit for each item in the wave. This saves about 4 instructions when and/or/xoring any condition, and also helps write conditions that need to be passed in vcc. This should work correctly now that the SGPR live range fixing pass works. More work is needed to eliminate the VReg_1 pseudo regclass and possibly the entire SILowerI1Copies pass. llvm-svn: 223206
* R600/SI: Fix suspicious indexingMatt Arsenault2014-12-031-5/+7
| | | | | | | | The loop is over the operands of an instruction, and checks the register with the sub reg index of the dest register. This probably meant to be checking the sub reg index of the same operand. llvm-svn: 223205
* R600/SI: Fix running SILowerI1Copies a second timeMatt Arsenault2014-12-031-2/+1
| | | | llvm-svn: 223204
* R600/SI: Fix live range error hidden by SIFoldOperandsMatt Arsenault2014-12-031-0/+9
| | | | | | | | | | | | | | | m0 is treated as a virtual register class with a single register rather than the physical register it really is. This was updating the live range of the used virtual copy of m0 from the first ds_read instruction, and leaving the unused copy unchanged. This resulted in a "Live segment doesn't end at a valid instruction" verifier error because the erased instructions. Update the live range of the second copy (which should be dead). No test since I'm not sure how to trigger this with SIFoldOperands enabled. llvm-svn: 223203
* R600/SI: Enable inline assemblyTom Stellard2014-12-031-2/+1
| | | | | | | | We just needed to remove the assertion in AMDGPURegisterInfo::getFrameRegister(), which is called when initializing the parser for inline assembly. llvm-svn: 223197
* R600/SI: Change mubuf offsets to print as decimalMatt Arsenault2014-12-031-1/+1
| | | | | | This matches SC's behavior. llvm-svn: 223194
* R600/SI: Emit amd_kernel_code_t header for AMDGPU environmentTom Stellard2014-12-025-1/+829
| | | | llvm-svn: 223160
* R600/SI: Move more information into SIProgramInfo structTom Stellard2014-12-023-50/+80
| | | | llvm-svn: 223154
* R600/SI: Refactor AMDGPUAsmPrinter::EmitProgramInfoSI()Tom Stellard2014-12-021-9/+11
| | | | llvm-svn: 223144
* R600/SI: Set correct number of user sgprs for HSA runtimeTom Stellard2014-12-021-1/+4
| | | | | | We don't support scratch buffers yet with HSA. llvm-svn: 223130
* R600/SI: Set the ATC bit on all resource descriptors for the HSA runtimeTom Stellard2014-12-026-9/+33
| | | | llvm-svn: 223125
* R600/SI: Various instruction format bit test cleanupsMatt Arsenault2014-12-015-94/+134
| | | | | | | | | | | - Fix missing SALU format bits - Remove unused isSALUInstr - Add isVALU - Switch isDS to use a bit like the others - Move SIInstrInfo::is* functions to header - Reorder so they are approximately sorted by type (SALU, VALU, memory) llvm-svn: 223038
* R600/SI: Fix assertion on sign extend of 3 vectorsMatt Arsenault2014-11-281-2/+2
| | | | | | | This was trying to create an MVT with 3x vectors which created an invalid EVT llvm-svn: 222942
* R600/SI: Use ZeroOrNegativeOneBooleanContentMatt Arsenault2014-11-262-2/+3
| | | | | | | | | | | | | | This sort of doesn't matter since the setcc type is i1, but this previously was using the default UndefinedBooleanContent. This makes it more consistent with R600. This enables more optimizations which typically give up on UndefinedBooleanContent. For example, there is already a special case target DAG combine for setcc + sext which can be eliminated in favor of what the generic DAG combiner can do if it assumes boolean values are sign extended. Since -1 is an inline immediate, using it is basically free and the backend already uses it when a boolean value is needed in a wider type. llvm-svn: 222850
* R600/SI: Create e64 versions of and/or/xor in SILowerI1CopiesMatt Arsenault2014-11-261-3/+3
| | | | | | | | | This fixes moving boolean constants into registers before operating on them. They get permuted and shrunk down to e32 anyway later. This is a temporary fix until the patch that removes these pseudos is committed. llvm-svn: 222844
* Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.Craig Topper2014-11-262-2/+2
| | | | llvm-svn: 222801
* R600/SI: Only use one DEBUG()Matt Arsenault2014-11-251-2/+1
| | | | llvm-svn: 222789
* Revert r222746: That commit did not update any tests and caused two R600Chandler Carruth2014-11-251-2/+1
| | | | | | | | tests to start failing. Original commit log: R600/SI: Disable commutativity for MIN/MAX_LEGACY llvm-svn: 222753
* R600/SI: Disable commutativity for MIN/MAX_LEGACYMarek Olsak2014-11-251-1/+2
| | | | llvm-svn: 222746
* R600/SI: Fix allocating flat_scr_lo / flat_scr_hiMatt Arsenault2014-11-251-0/+2
| | | | | | | | Only the super register flat_scr was marked as reserved, so in some cases with high register usage it would still try to allocate the subregisters. llvm-svn: 222737
* Removing a variable that is initialized but never read. The original author ↵Aaron Ballman2014-11-241-6/+2
| | | | | | has been alerted to the warning, in case this variable is meant to be used. Fixes -Werror builds in the meantime. llvm-svn: 222649
* R600: Fix extloads of i1 on R600/EvergreenMatt Arsenault2014-11-231-0/+5
| | | | llvm-svn: 222631
* R600: Fix assert on copy of an i1 on pre-SIMatt Arsenault2014-11-231-1/+2
| | | | | | | i1 is not a legal type on Evergreen, so this combine proceeded and tried to produce a bitcast between i1 and i8. llvm-svn: 222630
* R600/SI: Add an s_mov_b32 to patterns which use the M0RegClassTom Stellard2014-11-212-24/+8
| | | | | | | We need to use a s_mov_b32 rather than a copy, so that CSE will eliminate redundant moves to the m0 register. llvm-svn: 222584
* R600/SI: Emit s_mov_b32 m0, -1 before every DS instructionTom Stellard2014-11-216-40/+28
| | | | | | | | | | | | This s_mov_b32 will write to a virtual register from the M0Reg class and all the ds instructions now take an extra M0Reg explicit argument. This change is necessary to prevent issues with the scheduler mixing together instructions that expect different values in the m0 registers. llvm-svn: 222583
* R600/SI: Add SIFoldOperands passTom Stellard2014-11-214-0/+209
| | | | | | | This pass attempts to fold the source operands of mov and copy instructions into their uses. llvm-svn: 222581
* R600/SI: Mark s_mov_b32 and s_mov_b64 as rematerializableTom Stellard2014-11-211-0/+2
| | | | llvm-svn: 222579
* R600/SI: Make SIInstrInfo::isOperandLegal() more strictTom Stellard2014-11-191-1/+10
| | | | | | | | | | | | A register operand that has a common sub-class with its instruction's defined register class is not always legal. For example, SReg_32 and M0Reg both have a common sub-class, but we can't use an SReg_32 in instructions that expect a M0Reg. This prevents the llvm.SI.sendmsg.ll test from failing when the fold operand pass is added. llvm-svn: 222368
* R600/SI: Implement areMemAccessesTriviallyDisjointMatt Arsenault2014-11-192-0/+91
| | | | | | | | | This partially makes up for not having address spaces used for alias analysis in some simple cases. This is not yet enabled by default so shouldn't change anything yet. llvm-svn: 222286
* R600/SI: Set hasSideEffects = 0 on load and store instructions.Matt Arsenault2014-11-182-4/+9
| | | | | | | | | | Assuming unmodeled side effects interferes with some scheduling opportunities. Don't put it in the base class of DS instructions since there are a few weird effecting, non load/store instructions there. llvm-svn: 222285
* R600/SI: Move SIFixSGPRCopies to inst selector passesMatt Arsenault2014-11-181-7/+9
| | | | | | | | | | | | This should expose more of the actually used VALU instructions to the machine optimization passes. This also should help getting i1 handling into a better state. For not entirly understood reasons, this fixes the split-scalar-i64-add.ll test where a 64-bit add would only partially be moved to the VALU resulting in use of undefined VCC. llvm-svn: 222256
* R600/SI: Make sure resource descriptors are always stored in SGPRsTom Stellard2014-11-181-2/+2
| | | | llvm-svn: 222253
* R600/SI: Don't copy flags when extracting subregMatt Arsenault2014-11-171-6/+8
| | | | | | | | | This was resulting in use of a register after a kill. For some reason this showed up as a problem in many tests when moving the SIFixSGPRCopies pass closer to instruction selection. llvm-svn: 222175
* R600/SI: Assume SIFixSGPRCopies makes changesMatt Arsenault2014-11-171-1/+2
| | | | | | I'm not sure if this was breaking anything. llvm-svn: 222174
* Convert some EVTs to MVTs where only a SimpleValueType is needed.Craig Topper2014-11-161-1/+1
| | | | llvm-svn: 222109
* R600: Permute operands when selecting legacy min/maxMatt Arsenault2014-11-151-6/+9
| | | | | | | | | | This gets the correct NaN behavior based on the compare type the hardware uses. This now passes the new piglit test I have for this on SI. Add stricter tests for the operand order. llvm-svn: 222079
* R600: Fix 64-bit integer divisionTom Stellard2014-11-151-2/+2
| | | | | | | | This fixes a failure in one of the oclconform tests. Patch by: Jan Vesely llvm-svn: 222073
* R600: Factor i64 UDIVREM lowering into its own fuctionTom Stellard2014-11-153-68/+84
| | | | | | | | This is so it could potentially be used by SI. However, the current implementation does not always produce correct results, so the IntegerDivisionPass is being used instead. llvm-svn: 222072
* R600/SI: Mark s_movk_i32 as rematerializableTom Stellard2014-11-141-0/+2
| | | | llvm-svn: 222037
* R600/SI: Fix spilling of m0 registerTom Stellard2014-11-141-1/+9
| | | | | | | | | | If we have spilled the value of the m0 register, then we need to restore it with v_readlane_b32 to a regular sgpr, because v_readlane_b32 can't write to m0. v_readlane_b32 can't write to m0, so llvm-svn: 222036
* R600/SI: Combine min3/max3 instructionsMatt Arsenault2014-11-146-10/+135
| | | | llvm-svn: 222032
* R600/SI: Fix verifier error from a branch on IMPLICIT_DEFMatt Arsenault2014-11-141-0/+8
| | | | | | SIILowerI1Copies wasn't correctly handling this case. llvm-svn: 222020
* Fix unused variable warning without assertsMatt Arsenault2014-11-141-0/+2
| | | | llvm-svn: 222017
* R600/SI: Match integer min / max instructionsMatt Arsenault2014-11-142-29/+86
| | | | llvm-svn: 222015
* R600/SI: Use S_BFE_I64 for 64-bit sext_inregMatt Arsenault2014-11-145-17/+82
| | | | llvm-svn: 222012
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