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* R600/SI: Allow commuting with source modifiersMatt Arsenault2014-10-171-11/+22
| | | | llvm-svn: 220066
* R600/SI: Simplify code with hasModifiersSetMatt Arsenault2014-10-171-9/+8
| | | | llvm-svn: 220065
* R600/SI: Fix general commuting breaking src modsMatt Arsenault2014-10-172-1/+22
| | | | | | | | The generic code trying to use findCommutedOpIndices won't understand that it needs to swap the modifier operands also, so it should fail if they are set. llvm-svn: 220064
* R600/SI: Cleanup code with ChangeToFPImmediateMatt Arsenault2014-10-171-4/+3
| | | | llvm-svn: 220063
* R600/SI: Allow comuting fp immediatesMatt Arsenault2014-10-171-3/+9
| | | | llvm-svn: 220062
* R600/SI: Use early return instead of checking condition twiceMatt Arsenault2014-10-171-11/+16
| | | | | | Any commutable instruction will have at least src1. llvm-svn: 220061
* R600/SI: Use complex pattern for MUBUF load patterns.Matt Arsenault2014-10-171-3/+2
| | | | | | This eliminates a use of the SI_ADDR64_RSRC pseudo llvm-svn: 220057
* R600/SI: Remove SI_BUFFER_RSRC pseudoMatt Arsenault2014-10-173-42/+23
| | | | | | | Just use REG_SEQUENCE directly, so there are fewer instructions to need to deal with later. llvm-svn: 220056
* R600/SI: Simplify debug printingMatt Arsenault2014-10-171-5/+3
| | | | llvm-svn: 219999
* R600/SI: Remove another VALU patternMatt Arsenault2014-10-161-5/+0
| | | | llvm-svn: 219988
* R600/SI: Remove unnecessary VALU patternsMatt Arsenault2014-10-161-41/+0
| | | | | | | | These haven't been necessary since allowing selecting SALU instructions in non-entry blocks was enabled. llvm-svn: 219956
* R600: Fix nonsensical implementation of computeKnownBits for BFEMatt Arsenault2014-10-161-5/+1
| | | | | | This was resulting in invalid simplifications of sdiv llvm-svn: 219953
* R600: Remove dead functionMatt Arsenault2014-10-162-15/+0
| | | | llvm-svn: 219879
* R600: Remove unnecessary part of computeKnownBitsForTargetNodeMatt Arsenault2014-10-151-5/+0
| | | | | | | Zero-width BFEs are combined away already, so there's no point in handling them. llvm-svn: 219868
* Move variable down to useMatt Arsenault2014-10-151-4/+4
| | | | llvm-svn: 219867
* R600/SI: Fix bug where immediates were being used in DS addr operandsTom Stellard2014-10-151-1/+4
| | | | | | | | | | | | | | | | | | | The SelectDS1Addr1Offset complex pattern always tries to store constant lds pointers in the offset operand and store a zero value in the addr operand. Since the addr operand does not accept immediates, the zero value needs to first be copied to a register. This newly created zero value will not go through normal instruction selection, so we need to manually insert a V_MOV_B32_e32 in the complex pattern. This bug was hidden by the fact that if there was another zero value in the DAG that had not been selected yet, then the CSE done by the DAG would use the unselected node for the addr operand rather than the one that was just created. This would lead to the zero value being selected and the DAG automatically inserting a V_MOV_B32_e32 instruction. llvm-svn: 219848
* R600/SI: Also try to use 0 base for misaligned 8-byte DS loads.Matt Arsenault2014-10-151-0/+17
| | | | llvm-svn: 219823
* R600: Fix miscompiles when BFE has multiple usesMatt Arsenault2014-10-151-7/+10
| | | | | | SimplifyDemandedBits would break the other uses of the operand. llvm-svn: 219819
* Simplify handling of --noexecstack by using getNonexecutableStackSection.Rafael Espindola2014-10-151-6/+3
| | | | llvm-svn: 219799
* Move getNonexecutableStackSection up to the base ELF class.Rafael Espindola2014-10-152-6/+0
| | | | | | The .note.GNU-stack section is not SystemZ/X86 specific. llvm-svn: 219796
* R600: Use existing variableMatt Arsenault2014-10-151-1/+1
| | | | llvm-svn: 219778
* R600: Remove outdated commentMatt Arsenault2014-10-151-3/+0
| | | | llvm-svn: 219777
* Reapply "R600: Add new intrinsic to read work dimensions"Jan Vesely2014-10-143-5/+20
| | | | | | | | | This effectively reverts revert 219707. After fixing the test to work with new function name format and renamed intrinsic. Reviewed-by: Tom Stellard <tom@stellard.net> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 219710
* Revert "R600: Add new intrinsic to read work dimensions"Rafael Espindola2014-10-143-20/+5
| | | | | | | | This reverts commit r219705. CodeGen/R600/work-item-intrinsics.ll was failing on linux. llvm-svn: 219707
* R600: Add new intrinsic to read work dimensionsJan Vesely2014-10-143-5/+20
| | | | | | | | | | | | | | v2: Add SI lowering Add test v3: Place work dimensions after the kernel arguments. v4: Calculate offset while lowering arguments v5: rebase v6: change prefix to AMDGPU Reviewed-by: Tom Stellard <tom@stellard.net> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 219705
* R600: FMA is VecALU only instructionJan Vesely2014-10-141-1/+1
| | | | | | Reviewed-by: Tom Stellard <tom@stellard.net> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 219704
* R600/SI: Use DS offsets for constant addressesMatt Arsenault2014-10-141-0/+12
| | | | | | | | Use 0 as the base address for a constant address, so if we have a constant address we can save moves and form read2/write2s. llvm-svn: 219698
* R600/SI: Minor cleanup of functionMatt Arsenault2014-10-131-9/+11
| | | | llvm-svn: 219616
* R600/SI: Change how DS offsets are printedMatt Arsenault2014-10-103-16/+61
| | | | | | | Match SC by using offset/offset0/offset1 and printing in decimal. llvm-svn: 219537
* R600/SI: Match read2/write2 stride 64 versionsMatt Arsenault2014-10-101-38/+80
| | | | llvm-svn: 219536
* R600/SI: Add load / store machine optimizer pass.Matt Arsenault2014-10-107-1/+403
| | | | | | | | | | | | | Currently this only functions to match simple cases where ds_read2_* / ds_write2_* instructions can be used. In the future it might match some of the other weird load patterns, such as direct to LDS loads. Currently enabled only with a subtarget feature to enable easier testing. llvm-svn: 219533
* R600/SI: Disable copying of SCCMatt Arsenault2014-10-101-1/+5
| | | | llvm-svn: 219519
* Fix typoMatt Arsenault2014-10-091-3/+3
| | | | llvm-svn: 219429
* R600/SI: Legalize CopyToReg during instruction selectionTom Stellard2014-10-093-14/+20
| | | | | | | The instruction emitter will crash if it encounters a CopyToReg node with a non-register operand like FrameIndex. llvm-svn: 219428
* R600/SI: Legalize INSERT_SUBREG instructions during PostISelFoldingTom Stellard2014-10-091-0/+29
| | | | | | | | LLVM assumes INSERT_SUBREG will always have register operands, so we need to legalize non-register operands, like FrameIndexes, to avoid random assertion failures. llvm-svn: 219420
* Remove unused argument to CreateTargetScheduleState and changeEric Christopher2014-10-092-7/+6
| | | | | | | the TargetMachine to a TargetSubtargetInfo since everything we wanted is off of that. llvm-svn: 219382
* R600/SI: Refactor VOP3 instruction defsTom Stellard2014-10-072-61/+64
| | | | llvm-svn: 219256
* R600/SI: Refactor VOPC instruction defsTom Stellard2014-10-072-213/+217
| | | | llvm-svn: 219255
* R600/SI: Refactor VOP2 instruction defsTom Stellard2014-10-072-42/+46
| | | | llvm-svn: 219254
* R600/SI: Refactor VOP1 instruction defsTom Stellard2014-10-073-72/+96
| | | | llvm-svn: 219253
* R600: Remove dead codeMatt Arsenault2014-10-072-18/+1
| | | | llvm-svn: 219242
* R600: Remove some redundant initializations from AMDGPUMCAsmInfoTom Stellard2014-10-071-10/+0
| | | | llvm-svn: 219238
* R600: Use MCAsmInfoELF as AMDGPUMCAsmInfo base classTom Stellard2014-10-072-3/+8
| | | | | | | | | | | | | The main reason for this is that the MCAsmInfo class, which we were previously using as the base class, sets PrivateGlobalPrefix to "L", which causes all global functions that start with L to be treated as local symbols. MCAsmInfoELF sets PrivateGlobalPrefix to ".L", which is what we want, and it is probably a good idea to use this as the base class anyway, since we are emitting ELF binaries. llvm-svn: 219237
* R600/SI: Remove assertion in SIInstrInfo::areLoadsFromSameBasePtr()Tom Stellard2014-10-071-1/+4
| | | | | | | Added a FIXME coment instead, we need to handle the case where the two DS instructions being compared have different numbers of operands. llvm-svn: 219236
* Remove unnecessary copying or replace it with moves in a bunch of places.Benjamin Kramer2014-10-042-10/+10
| | | | | | NFC. llvm-svn: 219061
* R600/SI: Custom lower f64 -> i64 conversionsMatt Arsenault2014-10-033-3/+57
| | | | llvm-svn: 219038
* R600: Custom lower [s|u]int_to_fp for i64 -> f64Matt Arsenault2014-10-033-2/+46
| | | | llvm-svn: 219037
* R600/SI: Fix ftrunc f64 conformance failures.Matt Arsenault2014-10-031-1/+1
| | | | | | Re-add the tests since they were deleted at some point llvm-svn: 219036
* R600: Align functions to 256 bytesTom Stellard2014-10-032-3/+12
| | | | llvm-svn: 219002
* Eliminate some deep std::vector copies. NFC.Benjamin Kramer2014-10-033-6/+5
| | | | llvm-svn: 218999
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