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* R600/SI: Fix assembly names for exec_hi and exec_loTom Stellard2014-11-141-2/+2
| | | | llvm-svn: 221995
* R600/SI: Start implementing an assemblerTom Stellard2014-11-1413-30/+413
| | | | | | | This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994
* R600/SI: Make constant array staticMatt Arsenault2014-11-141-1/+1
| | | | llvm-svn: 221965
* R600/SI: Fix fmin_legacy / fmax_legacy matching for SIMatt Arsenault2014-11-135-33/+75
| | | | | | select_cc is expanded on SI, so this was never matched. llvm-svn: 221941
* We can get the TLOF from the TargetMachine - so constructor no longer ↵Aditya Nandakumar2014-11-131-1/+1
| | | | | | requires TargetLoweringObjectFile to be passed. llvm-svn: 221926
* R600/SI: Use s_movk_i32Matt Arsenault2014-11-133-2/+17
| | | | llvm-svn: 221922
* R600/SI: Fix definition for s_cselect_b32Matt Arsenault2014-11-132-3/+7
| | | | | | | | | | | These were directly using the old base instruction class, and specifying the wrong register classes for operands. The operands can be the other special inputs besides SGPRs. The op name was also being directly used for the asm string, so this was printed without any operands. llvm-svn: 221921
* R600: Fix assert on empty functionMatt Arsenault2014-11-131-1/+0
| | | | | | | | If a function is just an unreachable, this would hit a "this is not a MachO target" assertion because of setting HasSubsectionViaSymbols. llvm-svn: 221920
* R600: Error on initializer for LDS.Matt Arsenault2014-11-131-2/+21
| | | | | | Also give a proper error for other address spaces. llvm-svn: 221917
* R600/SI: Get rid of FCLAMP_SI pseudoMatt Arsenault2014-11-134-25/+16
| | | | | | | It's not necessary. Also use complex patterns to allow src modifier usage. llvm-svn: 221916
* R600/SI: Allow commuting with src2_modifiersMatt Arsenault2014-11-131-5/+0
| | | | llvm-svn: 221911
* R600/SI: Allow commuting some 3 op instructionsMatt Arsenault2014-11-131-3/+27
| | | | | | | | | | | | | e.g. v_mad_f32 a, b, c -> v_mad_f32 b, a, c This simplifies matching v_madmk_f32. This looks somewhat surprising, but it appears to be OK to do this. We can commute src0 and src1 in all of these instructions, and that's all that appears to matter. llvm-svn: 221910
* This patch changes the ownership of TLOF from TargetLoweringBase to ↵Aditya Nandakumar2014-11-133-1/+8
| | | | | | TargetMachine so that different subtargets could share the TLOF effectively llvm-svn: 221878
* Fix broken doxygen annotations, NFCJingyue Wu2014-11-121-2/+0
| | | | llvm-svn: 221801
* Revert "IR: MDNode => Value"Duncan P. N. Exon Smith2014-11-111-2/+1
| | | | | | | | | | | | | | | | | Instead, we're going to separate metadata from the Value hierarchy. See PR21532. This reverts commit r221375. This reverts commit r221373. This reverts commit r221359. This reverts commit r221167. This reverts commit r221027. This reverts commit r221024. This reverts commit r221023. This reverts commit r220995. This reverts commit r220994. llvm-svn: 221711
* R600: Remove unused defineMatt Arsenault2014-11-071-2/+0
| | | | llvm-svn: 221543
* R600/SI: Fix omod display for VOP3bMatt Arsenault2014-11-051-1/+1
| | | | llvm-svn: 221387
* R600/SI: Move all rsrc building functions to SIISelLoweringMatt Arsenault2014-11-053-50/+61
| | | | llvm-svn: 221383
* R600/SI: Remove SI_ADDR64_RSRCMatt Arsenault2014-11-054-44/+62
| | | | llvm-svn: 221382
* R600/SI: Change all instruction assembly names to lowercase.Tom Stellard2014-11-052-859/+859
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matches the format produced by the AMD proprietary driver. //==================================================================// // Shell script for converting .ll test cases: (Pass the .ll files you want to convert to this script as arguments). //==================================================================// ; This was necessary on my system so that A-Z in sed would match only ; upper case. I'm not sure why. export LC_ALL='C' TEST_FILES="$*" MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r` for f in $TEST_FILES; do # Check that there are SI tests: grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f if [ $? -eq 0 ]; then for match in $MATCHES; do sed -i -e "s/\([ :]$match\)/\L\1/" $f done # Try to get check lines with partial instruction names sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f fi done sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll //==================================================================// // Shell script for converting .td files (run this last) //==================================================================// export LC_ALL='C' sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td llvm-svn: 221350
* R600/SI: Rename div_scale dest operands to match documentationMatt Arsenault2014-11-041-2/+2
| | | | llvm-svn: 221291
* R600/LLVMBuild.txt: Add TransformUtils.NAKAMURA Takumi2014-11-041-1/+1
| | | | llvm-svn: 221228
* Reapply: R600: Make sure to inline all internal functionsTom Stellard2014-11-034-0/+82
| | | | | | | | Function calls aren't supported yet. This was reverted due to build breakages, which should be fixed now. llvm-svn: 221173
* IR: MDNode => Value: Instruction::getAllMetadataOtherThanDebugLoc()Duncan P. N. Exon Smith2014-11-031-1/+2
| | | | | | | Change `Instruction::getAllMetadataOtherThanDebugLoc()` from a vector of `MDNode` to one of `Value`. Part of PR21433. llvm-svn: 221167
* R600: Don't unnecessarily repeat the register classMatt Arsenault2014-11-021-5/+5
| | | | llvm-svn: 221119
* R600/SI: Use REG_SEQUENCE instead of INSERT_SUBREGsMatt Arsenault2014-11-024-47/+43
| | | | llvm-svn: 221118
* Support REG_SEQUENCE in tablegen.Matt Arsenault2014-11-021-3/+3
| | | | | | | | | The problem is mostly that variadic output instruction aren't handled, so it is rejected for having an inconsistent number of operands, and then the right number of operands isn't emitted. llvm-svn: 221117
* Revert "R600: Add missing file to CMakeLists.txt"Reid Kleckner2014-10-311-1/+0
| | | | | | | | This reverts commit r220998. It should've been reverted with the other change. llvm-svn: 221021
* Revert "R600: Make sure to inline all internal functions"Reid Kleckner2014-10-313-81/+0
| | | | | | | | | This reverts commit r220996. It introduced layering violations causing link errors in many configurations. llvm-svn: 221020
* Work around bugs in MSVC "14" CTP 3's conversion logicReid Kleckner2014-10-311-2/+2
| | | | | | | | | | It appears to ignore or find ambiguous MachineInstrBuilder's conversion operators that allow conversion to MachineInstr* and MachineBasicBlock::bundle_iterator. As a workaround, add an explicit way to get the MachineInstr. llvm-svn: 221017
* R600: Add IPO to the list of required librariesTom Stellard2014-10-311-1/+1
| | | | llvm-svn: 221004
* R600: Add missing file to CMakeLists.txtTom Stellard2014-10-311-0/+1
| | | | llvm-svn: 220998
* R600: Don't promote allocas when one of the users is a ptrtoint instructionTom Stellard2014-10-311-6/+19
| | | | | | | | We need to figure out how to track ptrtoint values all the way until result is converted back to a pointer in order to correctly rewrite the pointer type. llvm-svn: 220997
* R600: Make sure to inline all internal functionsTom Stellard2014-10-313-0/+81
| | | | | | Function calls aren't supported yet. llvm-svn: 220996
* Add minnum / maxnum codegenMatt Arsenault2014-10-213-4/+12
| | | | llvm-svn: 220342
* R600/SI: Add missing parameter to div_fmas intrinsicMatt Arsenault2014-10-211-0/+2
| | | | llvm-svn: 220338
* R600: Use default GlobalDirectiveMatt Arsenault2014-10-211-1/+0
| | | | | | | The overridden one wasn't inserting a space, so you would end up with .globalfoo llvm-svn: 220329
* Drop support for an old version of ld64 (from darwin 9).Rafael Espindola2014-10-211-1/+0
| | | | llvm-svn: 220310
* R600/SI: Add pattern for bswapMatt Arsenault2014-10-213-0/+19
| | | | llvm-svn: 220304
* Fix a bit of confusion about .set and produce more readable assembly.Rafael Espindola2014-10-211-1/+0
| | | | | | | | | | | | | | | Every target we support has support for assembly that looks like a = b - c .long a What is special about MachO is that the above combination suppresses the production of a relocation. With this change we avoid producing the intermediary labels when they don't add any value. llvm-svn: 220256
* R600/SI: Add global atomicrmw xchgAaron Watry2014-10-172-0/+4
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220110
* R600/SI: Add global atomicrmw xorAaron Watry2014-10-172-1/+4
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220109
* R600/SI: Add global atomicrmw orAaron Watry2014-10-172-1/+4
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220108
* R600/SI: Add global atomicrmw min/uminAaron Watry2014-10-172-2/+8
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220107
* R600/SI: Add global atomicrmw max/umaxAaron Watry2014-10-172-2/+8
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220106
* R600/SI: Add global atomicrmw andAaron Watry2014-10-172-1/+4
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220105
* R600/SI: Add global atomicrmw subAaron Watry2014-10-172-1/+4
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220104
* R600/SI: Remove redundant setting of instruction bitsMatt Arsenault2014-10-171-4/+0
| | | | | | These are all set on the instruction base classes. llvm-svn: 220091
* Fix typoMatt Arsenault2014-10-171-1/+1
| | | | llvm-svn: 220068
* R600/SI: Also check for FPImm literal constantsMatt Arsenault2014-10-171-1/+1
| | | | llvm-svn: 220067
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