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* R600: Remove leftover code in R600MachineScheduler.cppVincent Lejeune2013-06-061-16/+0
| | | | | | Spotted by Benjamin Kramer. llvm-svn: 183413
* Cast to the correct type. Pointer, not reference.Bill Wendling2013-06-061-1/+1
| | | | llvm-svn: 183385
* R600OptimizeVectorRegisters.cpp: Tweak a warning. [-Wsometimes-uninitialized]NAKAMURA Takumi2013-06-061-1/+1
| | | | | FIXME: Is it false alarm? llvm-svn: 183371
* R600OptimizeVectorRegisters.cpp: Suppress a warning. [-Wunused-variable]NAKAMURA Takumi2013-06-061-0/+1
| | | | llvm-svn: 183370
* Trailing linefeed.NAKAMURA Takumi2013-06-061-1/+0
| | | | llvm-svn: 183369
* Cast to the proper type.Bill Wendling2013-06-061-1/+1
| | | | llvm-svn: 183365
* R600: Replace predicate loop with predicate functionTom Stellard2013-06-051-11/+13
| | | | llvm-svn: 183351
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-054-0/+370
| | | | | | | Previously commited @183279 but tests were failing, reverted @183286 It was broken because @183336 was missing, now it's there. llvm-svn: 183343
* R600: Schedule copy from phys register at beginning of blockVincent Lejeune2013-06-052-1/+32
| | | | | | It allows regalloc pass to remove them by trivially assigning associated reg llvm-svn: 183336
* R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard2013-06-053-4/+40
| | | | | Reviewed-by: vljn at ovi.com llvm-svn: 183294
* Revert "R600: Add a pass that merge Vector Register"Rafael Espindola2013-06-054-370/+0
| | | | | | This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing. llvm-svn: 183286
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-044-0/+370
| | | | llvm-svn: 183279
* R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune2013-06-045-47/+186
| | | | llvm-svn: 183278
* R600: Swizzle texture/export instructionsVincent Lejeune2013-06-042-20/+126
| | | | llvm-svn: 183229
* Silencing an MSVC warning about mixing bool and unsigned int.Aaron Ballman2013-06-041-1/+1
| | | | llvm-svn: 183176
* R600/SI: Add support for work item and work group intrinsicsTom Stellard2013-06-033-15/+88
| | | | llvm-svn: 183138
* R600/SI: Add a calling convention for compute shadersTom Stellard2013-06-033-9/+39
| | | | llvm-svn: 183137
* R600/SI: Custom lower i64 sign_extendTom Stellard2013-06-032-0/+19
| | | | llvm-svn: 183136
* R600/SI: Adjust some instructions' out register class after ISelTom Stellard2013-06-032-0/+52
| | | | | | | This is necessary to avoid generating VGPR to SGPR copies in some cases. llvm-svn: 183135
* R600/SI: Handle REG_SEQUENCE in fitsRegClass()Tom Stellard2013-06-031-3/+13
| | | | llvm-svn: 183134
* R600/SI: Handle nodes with glue results correctly ↵Tom Stellard2013-06-031-0/+16
| | | | | | SITargetLowering::foldOperands() llvm-svn: 183133
* R600/SI: Fixup CopyToReg register class in PostprocessISelDAG()Tom Stellard2013-06-031-5/+33
| | | | | | | | | | The CopyToReg nodes will sometimes try to copy a value from a VGPR to an SGPR. This kind of copy is not possible, so we need to detect VGPR->SGPR copies and do something else. The current strategy is to replace these copies with VGPR->VGPR copies and hope that all the users of CopyToReg can accept VGPRs as arguments. llvm-svn: 183132
* R600/SI: Add support for global loadsTom Stellard2013-06-033-4/+39
| | | | llvm-svn: 183131
* R600/SI: Rework MUBUF store instructionsTom Stellard2013-06-035-42/+71
| | | | | | | The lowering of stores is now mostly handled in the tablegen files. No more BUFFER_STORE nodes I generated during legalization. llvm-svn: 183130
* R600: 3 op instructions have no write bit but the result are store in PVVincent Lejeune2013-06-031-3/+1
| | | | llvm-svn: 183111
* R600: CALL_FS consumes a stack size entryVincent Lejeune2013-06-031-0/+1
| | | | llvm-svn: 183108
* R600: use capital letter for PV channelVincent Lejeune2013-06-031-4/+4
| | | | llvm-svn: 183107
* R600: Constraints input regs of interp_xy,_zwVincent Lejeune2013-06-032-11/+15
| | | | llvm-svn: 183106
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-311-1/+2
| | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. llvm-svn: 183061
* Temporary fix to get rid of gcc warning.Patrik Hagglund2013-05-291-1/+10
| | | | llvm-svn: 182832
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-258-45/+44
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst regTom Stellard2013-05-231-2/+9
| | | | | | | | | Patch by: Vincent Lejeune https://bugs.freedesktop.org/show_bug.cgi?id=64877 NOTE: This is a candidate for the 3.3 branch. llvm-svn: 182600
* Move passes from namespace llvm into anonymous namespaces. Sort includes ↵Benjamin Kramer2013-05-2314-35/+35
| | | | | | while there. llvm-svn: 182594
* R600: Hide symbols of implementation details.Benjamin Kramer2013-05-234-63/+25
| | | | | | Also removes an unused function. llvm-svn: 182587
* Setting the default value (fixes CRT assertions about uninitialized variable ↵Aaron Ballman2013-05-231-3/+3
| | | | | | use when doing debug MSVC builds), and fixing coding style. llvm-svn: 182585
* Fix 32 bit build in c++11 mode.Rafael Espindola2013-05-231-1/+1
| | | | | | | | The error was: error: non-constant-expression cannot be narrowed from type 'long long' to 'long' in initializer list [-Wc++11-narrowing] MI.getOperand(6).getImm() & 0x1F, llvm-svn: 182584
* Fix a leak on the r600 backend.Rafael Espindola2013-05-232-8/+12
| | | | | | This should bring the valgrind bot back to life. llvm-svn: 182561
* clang-format this file.Rafael Espindola2013-05-231-29/+25
| | | | llvm-svn: 182560
* Fix use after free (pr16103).Rafael Espindola2013-05-221-7/+22
| | | | llvm-svn: 182482
* Check that a function starts with llvm. before using GET_FUNCTION_RECOGNIZER.Rafael Espindola2013-05-221-0/+3
| | | | | | Fixes a use of uninitialized memory found by asan and valgind. llvm-svn: 182480
* R600ISelLowering.cpp: Avoid "using namespace Intrinsic;" to appease MSC. ↵NAKAMURA Takumi2013-05-221-18/+15
| | | | | | | | Specify namespaces explicitly here. MSC is confused about "memcpy" between <cstring> and llvm::Intrinsic::memcpy, when llvm::Intrinsic were exposed. llvm-svn: 182452
* R600: Whitespace and untabify.NAKAMURA Takumi2013-05-221-2/+2
| | | | llvm-svn: 182451
* Create an FPOW SDNode opcode def in the target independent .td file rather ↵Owen Anderson2013-05-221-2/+0
| | | | | | than in a specific backend. llvm-svn: 182450
* Attempt to fix the mingw32 bot.Rafael Espindola2013-05-221-4/+4
| | | | | | | This should hopefully fix http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32 llvm-svn: 182446
* s/u_int32_t/uint32_t/Rafael Espindola2013-05-221-2/+2
| | | | llvm-svn: 182444
* Fix warning in non-assert build.Rafael Espindola2013-05-221-0/+2
| | | | llvm-svn: 182443
* R600: Fix bug detected by GCC warning.Benjamin Kramer2013-05-201-2/+2
| | | | | | | | | R600TextureIntrinsicsReplacer.cpp:232: warning: the address of ‘ArgsType’ will always evaluate as ‘true’ This doesn't have any effect on the output as a vararg intrinsic behaves the same way as a non-vararg one. llvm-svn: 182293
* R600/SI: Use a multiclass for MUBUF_Load_HelperTom Stellard2013-05-202-20/+30
| | | | | | | This will simplify the instructions and also the pattern definitions. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182288
* R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructionsTom Stellard2013-05-201-0/+1
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182287
* R600/SI: Add pattern for rotrTom Stellard2013-05-201-0/+2
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182286
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