summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/R600/SIInstructions.td
Commit message (Collapse)AuthorAgeFilesLines
...
* R600/SI: Fix schedule model for v_div_scale_{f32|f64}Matt Arsenault2015-02-141-1/+3
| | | | llvm-svn: 229235
* R600/SI: Add soffset operand to mubuf addr64 instructionTom Stellard2015-02-111-2/+2
| | | | | | We were previously hard-coding soffset to 0. llvm-svn: 228775
* R600/SI: Also enable WQM for image opcodes which calculate LOD v3Michel Danzer2015-02-061-32/+32
| | | | | | | | | | | | | If whole quad mode isn't enabled for these, the level of detail is calculated incorrectly for pixels along diagonal triangle edges, causing artifacts. v2: Use a TSFlag instead of lots of switch cases v3: Add test coverage Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88642 Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 228372
* R600/SI: Fix i64 truncate to i1Matt Arsenault2015-02-051-0/+6
| | | | llvm-svn: 228273
* R600/SI: Remove useless patterns in VALU which are already covered by SALUMarek Olsak2015-02-031-45/+16
| | | | | | | Also remove hasPostISelHook=1 from V_LSHL_B32. It's defined by InstSI already. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 228039
* R600/SI: Fix B64 VALU shifts on VIMarek Olsak2015-02-031-0/+14
| | | | | | | SI only has standard versions. VI only has REV versions. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 228037
* R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VIMarek Olsak2015-02-031-5/+5
| | | | | | | | | | | | | | | This can happen when a REV instruction is commuted. The trick is not to define the _vi versions of instructions, which has these consequences: - code generation will always fail if a pseudo cannot be lowered (very useful to catch bugs where an unsupported instruction somehow makes it to the printer) - ability to query if a pseudo can be lowered, which is done in commuteOpcode to prevent REV from commuting to non-REV on VI Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 227990
* R600/SI: Remove VOP2_REV definitions from target-specific instructionsMarek Olsak2015-02-031-6/+3
| | | | | | | | | | | The getCommute* functions are only used with pseudos, so this commit doesn't change anything. The issue with missing non-rev versions of shift instructions on VI will fixed separately. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 227989
* R600/SI: Trivial instruction definition corrections for VI (v2)Marek Olsak2015-02-031-12/+23
| | | | | | | | | | | | - V_MAC_LEGACY_F32 exists on VI, but it's VOP3-only. - Define CVT_PK opcodes which are different between SI and VI. These are unused. The idea is to define all chip differences. v2: keep V_MUL_LO_U32 Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 227988
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-301-5/+5
| | | | | | without a Function argument. llvm-svn: 227638
* R600/SI: Fix MIN3/MAX3 on VI, define MED3Marek Olsak2015-01-271-9/+16
| | | | llvm-svn: 227213
* R600/SI: Add VI versions of LDS atomicsMarek Olsak2015-01-271-73/+73
| | | | | | | Each class is split into two: one adds let statements around non-pseudos, and the other one specifies the parameters. llvm-svn: 227211
* R600/SI: Add VI versions of MUBUF atomicsMarek Olsak2015-01-271-42/+38
| | | | llvm-svn: 227210
* R600/SI: Add VI versions of MUBUF loads and storesMarek Olsak2015-01-271-36/+23
| | | | | | This enables a lot of existing patterns for VI. llvm-svn: 227209
* R600/SI: Use external symbols for scratch bufferTom Stellard2015-01-201-4/+4
| | | | | | | | We were passing the scratch buffer address to the shaders via user sgprs, but now we use external symbols and have the driver patch the shader using reloc information. llvm-svn: 226586
* R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32Matt Arsenault2015-01-151-2/+4
| | | | llvm-svn: 226230
* R600/SI: Unify VOP2 instructions which are VOP3-only on VIMarek Olsak2015-01-151-12/+11
| | | | | | | | | | | | | This removes some duplicated classes and definitions. These instructions are defined: _e32 // pseudo _e32_si _e64 // pseudo _e64_si _e64_vi llvm-svn: 226191
* R600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VIMarek Olsak2015-01-151-1/+1
| | | | llvm-svn: 226190
* R600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VIMarek Olsak2015-01-151-11/+11
| | | | | | | | These are VOP3-only on VI. The new multiclass doesn't define VOP3 versions of VOP2 instructions. llvm-svn: 226189
* R600/SI: Don't select SI-only VOP3 opcodes on VIMarek Olsak2015-01-151-17/+20
| | | | llvm-svn: 226186
* R600/SI: Spill VGPRs to scratch space for compute shadersTom Stellard2015-01-141-23/+28
| | | | llvm-svn: 225988
* R600/SI: Define a schedule modelTom Stellard2015-01-141-3/+51
| | | | | | | | The machine scheduler is still disabled by default. The schedule model is not complete yet, and could be improved. llvm-svn: 225913
* R600/SI: Add pattern for bitcasting fp immediates to integersTom Stellard2015-01-131-3/+3
| | | | | | | | The backend now assumes that all immediates are integers. This allows us to simplify immediate handling code, becasue we no longer need to handle fp and integer immediates differently. llvm-svn: 225844
* R600/SI: Remove VReg_32 register classTom Stellard2015-01-071-94/+94
| | | | | | | | | | | Use VGPR_32 register class instead. These two register classes were identical and having separate classes was causing SIInstrInfo::isLegalOperands() to be overly conservative in some cases. This change is necessary to prevent future paches from missing a folding opportunity in fneg-fabs.ll. llvm-svn: 225382
* R600/SI: Add a V_MOV_B64 pseudo instructionTom Stellard2015-01-071-0/+6
| | | | | | | This is used to simplify the SIFoldOperands pass and make it easier to fold immediates. llvm-svn: 225373
* R600/SI: Add class intrinsicMatt Arsenault2015-01-061-4/+4
| | | | llvm-svn: 225305
* R600/SI: Fix f64 inline immediatesMatt Arsenault2014-12-171-0/+5
| | | | llvm-svn: 224458
* R600: Fix min/max matching problems with unordered comparesMatt Arsenault2014-12-121-0/+2
| | | | | | | | The returned operand needs to be permuted for the unordered compares. Also fix incorrectly producing fmin_legacy / fmax_legacy for f64, which don't exist. llvm-svn: 224094
* R600/SI: Don't promote f32 select to i32Matt Arsenault2014-12-121-0/+5
| | | | | | | | This is nice for the instruction patterns, but it complicates min / max matching. The select doesn't have the correct type and would require looking through the bitcasts for the real float operands. llvm-svn: 224092
* R600/SI: Use unordered equal instructionsMatt Arsenault2014-12-111-2/+2
| | | | llvm-svn: 224067
* R600/SI: Make more unordered comparisons legalMatt Arsenault2014-12-111-8/+8
| | | | | | | This saves a second compare and an and / or by using the unordered comparison instructions. llvm-svn: 224066
* R600/SI: Use unordered not equal instructionsMatt Arsenault2014-12-111-2/+2
| | | | llvm-svn: 224065
* R600/SI: Set 20-bit immediate byte offset for SMRD on VIMarek Olsak2014-12-071-1/+41
| | | | llvm-svn: 223614
* R600/SI: Add VI instructionsMarek Olsak2014-12-071-490/+520
| | | | llvm-svn: 223603
* R600/SI: Add SCC Defs/Uses to SOP1 and SOP2 opcodesMarek Olsak2014-12-071-28/+49
| | | | llvm-svn: 223602
* R600/SI: Remove i1 pseudo VALU opsMatt Arsenault2014-12-031-23/+30
| | | | | | | | | | | | | | Select i1 logical ops directly to 64-bit SALU instructions. Vector i1 values are always really in SGPRs, with each bit for each item in the wave. This saves about 4 instructions when and/or/xoring any condition, and also helps write conditions that need to be passed in vcc. This should work correctly now that the SGPR live range fixing pass works. More work is needed to eliminate the VReg_1 pseudo regclass and possibly the entire SILowerI1Copies pass. llvm-svn: 223206
* Revert r222746: That commit did not update any tests and caused two R600Chandler Carruth2014-11-251-2/+1
| | | | | | | | tests to start failing. Original commit log: R600/SI: Disable commutativity for MIN/MAX_LEGACY llvm-svn: 222753
* R600/SI: Disable commutativity for MIN/MAX_LEGACYMarek Olsak2014-11-251-1/+2
| | | | llvm-svn: 222746
* R600/SI: Add an s_mov_b32 to patterns which use the M0RegClassTom Stellard2014-11-211-4/+8
| | | | | | | We need to use a s_mov_b32 rather than a copy, so that CSE will eliminate redundant moves to the m0 register. llvm-svn: 222584
* R600/SI: Emit s_mov_b32 m0, -1 before every DS instructionTom Stellard2014-11-211-7/+8
| | | | | | | | | | | | This s_mov_b32 will write to a virtual register from the M0Reg class and all the ds instructions now take an extra M0Reg explicit argument. This change is necessary to prevent issues with the scheduler mixing together instructions that expect different values in the m0 registers. llvm-svn: 222583
* R600/SI: Mark s_mov_b32 and s_mov_b64 as rematerializableTom Stellard2014-11-211-0/+2
| | | | llvm-svn: 222579
* R600/SI: Mark s_movk_i32 as rematerializableTom Stellard2014-11-141-0/+2
| | | | llvm-svn: 222037
* R600/SI: Combine min3/max3 instructionsMatt Arsenault2014-11-141-9/+21
| | | | llvm-svn: 222032
* R600/SI: Use S_BFE_I64 for 64-bit sext_inregMatt Arsenault2014-11-141-14/+9
| | | | llvm-svn: 222012
* R600/SI: Start implementing an assemblerTom Stellard2014-11-141-25/+30
| | | | | | | This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994
* R600/SI: Fix fmin_legacy / fmax_legacy matching for SIMatt Arsenault2014-11-131-2/+2
| | | | | | select_cc is expanded on SI, so this was never matched. llvm-svn: 221941
* R600/SI: Fix definition for s_cselect_b32Matt Arsenault2014-11-131-3/+2
| | | | | | | | | | | These were directly using the old base instruction class, and specifying the wrong register classes for operands. The operands can be the other special inputs besides SGPRs. The op name was also being directly used for the asm string, so this was printed without any operands. llvm-svn: 221921
* R600/SI: Get rid of FCLAMP_SI pseudoMatt Arsenault2014-11-131-11/+3
| | | | | | | It's not necessary. Also use complex patterns to allow src modifier usage. llvm-svn: 221916
* R600/SI: Allow commuting some 3 op instructionsMatt Arsenault2014-11-131-3/+27
| | | | | | | | | | | | | e.g. v_mad_f32 a, b, c -> v_mad_f32 b, a, c This simplifies matching v_madmk_f32. This looks somewhat surprising, but it appears to be OK to do this. We can commute src0 and src1 in all of these instructions, and that's all that appears to matter. llvm-svn: 221910
* R600/SI: Remove SI_ADDR64_RSRCMatt Arsenault2014-11-051-8/+0
| | | | llvm-svn: 221382
OpenPOWER on IntegriCloud