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path: root/llvm/lib/Target/R600/SIInstructions.td
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* R600/SI: add SETO/SETUO patternsChristian Konig2013-03-271-0/+14
| | | | | | | | 6 more piglit tests. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178145
* R600/SI: add cummuting of rev instructionsChristian Konig2013-03-271-15/+12
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178127
* R600/SI: add mulhu/mulhs patternsChristian Konig2013-03-271-1/+18
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178126
* R600/SI: add srl/sha patterns for SIChristian Konig2013-03-271-2/+6
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178125
* R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLEChristian Konig2013-03-261-13/+7
| | | | | | | Just define the address as unknown instead of VReg_32. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178022
* R600/SI: replace WQM intrinsicChristian Konig2013-03-261-11/+0
| | | | | | | Just enable WQM when we see an LDS interpolation instruction. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178019
* R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsicsMichel Danzer2013-03-221-2/+1
| | | | | | | | | | | | | | | | Fixes wrong lighting in some corner cases with r600g and radeonsi, e.g. manifested by failure of two piglit/glean tests and intermittent black patches in many apps. Tested on SI and RS880. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62012 [radeonsi] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58150 [r600g] NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 177730
* R600/SI: implement indirect adressing for SIChristian Konig2013-03-181-0/+69
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 177277
* R600/SI: add float vector typesChristian Konig2013-03-181-10/+71
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 177276
* R600/SI: add shl patternChristian Konig2013-03-181-1/+3
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 177275
* R600/SI: add BUFFER_LOAD_DWORD patternChristian Konig2013-03-181-3/+9
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 177274
* R600/SI: implement SI.load.const intrinsicChristian Konig2013-03-181-0/+12
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 177273
* R600/SI: enable all S_LOAD and S_BUFFER_LOAD opcodesChristian Konig2013-03-181-11/+25
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 177272
* R600/SI: rework input interpolation v2Christian Konig2013-03-071-61/+6
| | | | | | | | v2: update CMakeLists.txt as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176626
* R600/SI: remove SGPR address space v2Christian Konig2013-03-071-3/+2
| | | | | | | | v2: fix R600 regressions Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176624
* R600/SI: switch types of SGPRs to v*i8Christian Konig2013-03-071-2/+2
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176621
* R600/SI: remove S_MOV immediate patternsChristian Konig2013-03-011-12/+2
| | | | | | | They won't match anyway. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 176345
* R600/SI: add some more instruction flagsChristian Konig2013-02-261-14/+79
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176102
* R600/SI: add post ISel folding for SI v2Christian Konig2013-02-261-11/+11
| | | | | | | | | | Include immediate folding and SGPR limit handling for VOP3 instructions. v2: remove leftover hasExtraSrcRegAllocReq Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176101
* R600/SI: fix VOP3b encoding v2Christian Konig2013-02-261-6/+8
| | | | | | | | | | v2: document why we hardcode VCC for now. This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176099
* R600/SI: fix and cleanup SI register definition v2Christian Konig2013-02-261-2/+3
| | | | | | | | | | | | | | | | Prevent producing real strange tablegen code by using proper register sizes, alignments and hierarchy. Also cleanup the unused definitions and add some comments. v2: add SGPR 512 bit registers, stop registers from wrapping around, fix SGPR alignment This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176098
* R600/SI: Add pattern for sign extension of i1 to i32.Michel Danzer2013-02-221-0/+5
| | | | | | | | | 16 more little piglits with radeonsi. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175887
* R600/SI: Add pattern for logical or of i1 values.Michel Danzer2013-02-221-0/+4
| | | | | | | | | 24 more little piglits with radeonsi. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175886
* R600/SI: Add pattern for fceil.Michel Danzer2013-02-221-1/+3
| | | | | | | | | 9 more little piglits with radeonsi. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175885
* R600/SI: inline V_ADD|SUB_F32 patternsChristian Konig2013-02-211-9/+5
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175758
* R600/SI: replace IMPLICIT_DEF with SIOperand.ZEROChristian Konig2013-02-211-1/+1
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175757
* R600/SI: replace SI_V_CNDLT with a patternChristian Konig2013-02-211-7/+5
| | | | | | | | | | | It actually fixes quite a bunch of piglit tests. This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175756
* R600/SI: use patterns for clamp, fabs, fnegChristian Konig2013-02-211-4/+22
| | | | | | | | | | Instead of using custom inserters, it's simpler and should make DAG folding easier. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175755
* R600/SI: add all the other missing asm operands v2Christian Konig2013-02-211-22/+25
| | | | | | | | | v2: put implicit parameters in [] Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175754
* R600/SI: simplify VOPC_* pattern v2Christian Konig2013-02-211-248/+196
| | | | | | | | | | | Fixing asm operation names. v2: fix name of the e64 encoding, also add asm operands Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175750
* R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32Michel Danzer2013-02-211-1/+2
| | | | | | | NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175733
* R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad patternVincent Lejeune2013-02-181-2/+2
| | | | llvm-svn: 175446
* R600/SI: Add pattern to simplify i64 loadingChristian Konig2013-02-161-0/+5
| | | | | | | | This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175356
* R600/SI: nuke SReg_1 v3Christian Konig2013-02-161-31/+19
| | | | | | | | | | | | | | | | | It's completely unnecessary and can be replace with proper SReg_64 handling instead. This actually fixes a piglit test on SI. v2: use correct register class in addRegisterClass, set special classes as not allocatable v3: revert setting special classes as not allocateable This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175355
* R600/SI: cleanup literal handling v3Christian Konig2013-02-161-44/+37
| | | | | | | | | | | | | | | | Seems to be allot simpler, and also paves the way for further improvements. v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW, use VGPR0 in dummy EXP, avoid compiler warning, break after encoding the first literal. v3: correctly use V_ADD_F32_e64 This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175354
* R600/SI: replace AllReg_* with [SV]Src_* v2Christian Konig2013-02-161-64/+64
| | | | | | | | | | | | Mark all the operands that can also have an immediate. v2: SOFFSET is also an SSrc_32 operand This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175353
* R600/SI: Fix int_SI_fs_interp_constantMichel Danzer2013-02-141-11/+18
| | | | | | | | | | | | | | | | The important fix is that the constant interpolation value is stored in the parameter slot P0, which is encoded as 2. In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter slot as an operand to V_INTERP_MOV_F32 instead of hardcoding it there, and add a special operand class for the parameter slots for type checking and pretty printing. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175193
* R600/SI: Add pattern for mul.Tom Stellard2013-02-071-0/+4
| | | | | | | | | | 20 more little piglits with radeonsi. Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174654
* R600/SI: simplify and fix SMRD encodingTom Stellard2013-02-071-3/+36
| | | | | | | | | | The _SGPR variants where wrong. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174653
* R600/SI: add proper 64bit immediate support v2Tom Stellard2013-02-071-11/+8
| | | | | | | | | | v2: rebased on current upstream Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174652
* R600/SI: Use proper instructions for array/shadow samplers.Tom Stellard2013-02-071-3/+39
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174634
* R600/SI: Make sample intrinsic address parameter type overloaded.Tom Stellard2013-02-071-18/+34
| | | | | | | | | | | | | Handle vectors of 1 to 16 integers. Change the intrinsic names to prevent the wrong one from being selected at runtime due to the overloading. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174633
* R600/SI: Add basic support for more integer vector types.Tom Stellard2013-02-071-6/+10
| | | | | | | | | | | | | v1i32, v2i32, v8i32 and v16i32. Only add VGPR register classes for integer vector types, to avoid attempts copying from VGPR to SGPR registers, which is not possible. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174632
* R600/SI: Add pattern for flog2Michel Danzer2013-02-071-1/+3
| | | | | | | 22 more little piglits with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174615
* R600: Consolidate sub register indices.Tom Stellard2013-02-071-24/+24
| | | | | | | | | | Use sub0-15 everywhere. Patch by: Michel Dänzerr Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 174610
* R600/SI: Add patterns for fcos and fsin.Tom Stellard2013-02-051-0/+10
| | | | | | | | | | Fixes 37 piglit tests and allows e.g. FlightGear to run with radeonsi. Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174391
* R600/SI: Use unnormalized coordinates for sampling with the RECT target.Tom Stellard2013-01-211-0/+6
| | | | | | | | | Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 173053
* R600/SI: Take target parameter for sample intrinsics.Tom Stellard2013-01-211-3/+3
| | | | | | | | | Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 173052
* R600: Optimize and cleanup KILL on SITom Stellard2013-01-181-12/+12
| | | | | | | | | | | | We shouldn't insert KILL optimization if we don't have a kill instruction at all. Patch by: Christian König Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> llvm-svn: 172845
* R600: New control flow for SI v2Tom Stellard2012-12-191-15/+60
| | | | | | | | | | | | | | | | | | | | This patch replaces the control flow handling with a new pass which structurize the graph before transforming it to machine instruction. This has a couple of different advantages and currently fixes 20 piglit tests without a single regression. It is now a general purpose transformation that could be not only be used for SI/R6xx, but also for other hardware implementations that use a form of structurized control flow. v2: further cleanup, fixes and documentation Patch by: Christian König Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 170591
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