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* R600/SI: Convert v16i8 resource descriptors to i128Tom Stellard2013-08-141-38/+38
| | | | | | | | | | | | | Now that compute support is better on SI, we can't continue using v16i8 for descriptors since this is also a legal type in OpenCL. This patch fixes numerous hangs with the piglit OpenCL test and since we now use a target specific DAG node for LOAD_CONSTANT with the correct MemOperandFlags, this should also fix: https://bugs.freedesktop.org/show_bug.cgi?id=66805 llvm-svn: 188429
* R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2Tom Stellard2013-08-141-10/+0
| | | | | | | | | | | | Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG instructions should make it easier for the register allocator to coalasce unnecessary copies. v2: - Use an SGPR register class if all the operands of BUILD_VECTOR are SGPRs. llvm-svn: 188427
* R600/SI: Choose the correct MOV instruction for copying immediatesTom Stellard2013-08-141-0/+10
| | | | | | | | The instruction selector will now try to infer the destination register so it can decided whether to use V_MOV_B32 or S_MOV_B32 when copying immediates. llvm-svn: 188426
* R600/SI: Assign a register class to the $vaddr operand for MIMG instructionsTom Stellard2013-08-141-44/+68
| | | | | | | The previous code declared the operand as unknown:$vaddr, which made it possible for scalar registers to be used instead of vector registers. llvm-svn: 188425
* R600/SI: Handle MSAA texture targetsTom Stellard2013-08-141-1/+18
| | | | | | | Patch by: Marek Olšák Signed-off-by: Marek Olšák <marek.olsak@amd.com> llvm-svn: 188421
* R600/SI: Allow conversion between v32i8 and v8i32Tom Stellard2013-08-141-0/+5
| | | | | | | Patch by: Marek Olšák Signed-off-by: Marek Olšák <marek.olsak@amd.com> llvm-svn: 188420
* R600/SI: Add pattern for fp_to_uintTom Stellard2013-08-141-1/+3
| | | | | | | | | This fixes the F2U opcode for the Mesa driver. Patch by: Marek Olšák Signed-off-by: Marek Olšák <marek.olsak@amd.com> llvm-svn: 188418
* R600/SI: Add FMA patternNiels Ole Salscheider2013-08-101-2/+6
| | | | llvm-svn: 188135
* R600/SI: Implement fp32<->fp64 conversionsNiels Ole Salscheider2013-08-081-2/+6
| | | | llvm-svn: 187988
* R600/SI: Implement sint<->fp64 conversionsNiels Ole Salscheider2013-08-081-2/+6
| | | | llvm-svn: 187987
* R600: Implement TargetLowering::getVectorIdxTy()Tom Stellard2013-08-051-4/+4
| | | | | | | We use MVT::i32 for the vector index type, because we use 32-bit operations to caculate offsets when dynamically indexing vectors. llvm-svn: 187749
* R600: Add support for 24-bit MAD instructionsTom Stellard2013-07-231-2/+6
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186923
* R600: Add support for 24-bit MUL instructionsTom Stellard2013-07-231-4/+6
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186922
* R600: Improve support for < 32-bit loadsTom Stellard2013-07-231-7/+11
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186921
* R600: Clean up extended load patternsTom Stellard2013-07-231-1/+1
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186914
* R600/SI: Fix crash with VSELECTTom Stellard2013-07-181-0/+3
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=66175 llvm-svn: 186616
* R600/SI: Add support for v2f32 loadsTom Stellard2013-07-181-0/+1
| | | | llvm-svn: 186615
* R600/SI: Add support for v2f32 storesTom Stellard2013-07-181-0/+3
| | | | llvm-svn: 186614
* R600/SI: Add support for 64-bit loadsTom Stellard2013-07-151-1/+7
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=65873 llvm-svn: 186339
* R600/SI: Implement select and compares for SITom Stellard2013-07-121-6/+18
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186181
* R600/SI: Add fsqrt pattern for SITom Stellard2013-07-121-2/+6
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186180
* R600/SI: Add double precision fsub pattern for SITom Stellard2013-07-121-3/+14
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186179
* R600/SI: SI support for 64bit ConstantFPTom Stellard2013-07-121-0/+7
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186178
* R600/SI: Add initial double precision support for SITom Stellard2013-07-121-1/+29
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186177
* R600/SI: Initial local memory supportMichel Danzer2013-07-101-0/+15
| | | | | | | Enough for the radeonsi driver to use it for calculating derivatives. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186012
* R600/SI: Add pattern for the AMDGPU.barrier.local intrinsicMichel Danzer2013-07-101-1/+10
| | | | | | | lit test coverage to follow in the next commit. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186011
* R600/SI: Add intrinsic for retrieving the current thread IDMichel Danzer2013-07-101-2/+8
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186010
* R600/SI: Initial support for LDS/GDS instructionsMichel Danzer2013-07-101-0/+3
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186009
* R600/SI: Add intrinsics for texture sampling with user derivativesMichel Danzer2013-07-101-1/+6
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186008
* R600: Add SI load support for v[24]i32 and store for v2i32Tom Stellard2013-06-151-0/+5
| | | | | | | | | | | Also add a seperate vector lit test file, since r600 doesn't seem to handle v2i32 load/store yet, but we can test both for SI. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> llvm-svn: 184021
* R600: Rework subtarget info and remove AMDILDevice classesTom Stellard2013-06-071-2/+2
| | | | | | | | This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
* R600/SI: Add support for global loadsTom Stellard2013-06-031-1/+29
| | | | llvm-svn: 183131
* R600/SI: Rework MUBUF store instructionsTom Stellard2013-06-031-1/+38
| | | | | | | The lowering of stores is now mostly handled in the tablegen files. No more BUFFER_STORE nodes I generated during legalization. llvm-svn: 183130
* R600/SI: Use a multiclass for MUBUF_Load_HelperTom Stellard2013-05-201-9/+7
| | | | | | | This will simplify the instructions and also the pattern definitions. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182288
* R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructionsTom Stellard2013-05-201-0/+1
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182287
* R600/SI: Add pattern for rotrTom Stellard2013-05-201-0/+2
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182286
* R600/SI: Add patterns for 64-bit shift operationsTom Stellard2013-05-201-3/+9
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182284
* R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcodeTom Stellard2013-05-061-1/+12
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181269
* R600/SI: Add intrinsic for texture image loadingTom Stellard2013-05-061-8/+27
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181267
* R600/SI: Add pattern for uint_to_fpTom Stellard2013-05-061-1/+3
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181266
* R600/SI: Add patterns for integer maxima / minimaTom Stellard2013-05-061-4/+12
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181265
* R600/SI: Add pattern for AMDGPU.trunc intrinsicTom Stellard2013-05-061-1/+3
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181263
* R600: Add pattern for SHA-256 Ma functionTom Stellard2013-05-031-0/+6
| | | | | | This can be optimized using the BFI_INT instruction. llvm-svn: 181033
* R600: Use new tablegen syntax for patternsTom Stellard2013-05-021-208/+190
| | | | | | | | All but two patterns have been converted to the new syntax. The remaining two patterns will require COPY_TO_REGCLASS instructions, which the VLIW DAG Scheduler cannot handle. llvm-svn: 180922
* R600/SI: remove nonsense select patternTom Stellard2013-05-021-8/+1
| | | | | | | | Fortunately this pattern never matched, otherwise we would have generated incorrect code. Signed-off-by: Christian K??nig <christian.koenig@amd.com> llvm-svn: 180921
* R600: Add pattern for the BFI_INT instructionTom Stellard2013-04-191-0/+1
| | | | llvm-svn: 179830
* R600/SI: Use InstFlag for VOP3 modifier operandsTom Stellard2013-04-191-13/+12
| | | | | | | InstFlag has a default value of 0 and will simplify the VOP3 patterns. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 179829
* R600/SI: Add pattern for AMDGPUurecipMichel Danzer2013-04-101-2/+10
| | | | | | | 21 more little piglits with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 179186
* R600/SI: remove image sample writemaskChristian Konig2013-04-101-13/+12
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 179164
* R600/SI: Add support for buffer stores v2Tom Stellard2013-04-051-2/+8
| | | | | | | | v2: - Use the ADDR64 bit Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 178931
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