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* R600: Match sign_extend_inreg to BFE instructionsMatt Arsenault2014-03-171-2/+8
| | | | llvm-svn: 204072
* R600/SI: Use correct dest register class for V_READFIRSTLANE_B32Tom Stellard2014-03-171-1/+12
| | | | | | | | | | | | This instructions writes to an 32-bit SGPR. This change required adding the 32-bit VCC_LO and VCC_HI registers, because the full VCC register is 64 bits. This fixes verifier errors on several of the indirect addressing piglit tests. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 204055
* R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCCTom Stellard2014-03-071-6/+8
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 203281
* R600/SI: Optimize SI_KILL for constant operandsMichel Danzer2014-02-271-2/+2
| | | | | | | | If the SI_KILL operand is constant, we can either clear the exec mask if the operand is negative, or do nothing otherwise. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 202337
* R600/SI - Add new CI arithmetic instructions.Matt Arsenault2014-02-241-0/+52
| | | | | | | Does not yet include larger part required to match v_mad_i64_i32 / v_mad_u64_u32. llvm-svn: 202077
* R600/SI: Expand all v8[if]32 operationsTom Stellard2014-02-131-0/+2
| | | | llvm-svn: 201371
* R600/SI: Add a pattern for i32 anyextTom Stellard2014-02-131-2/+5
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 201370
* R600/SI: Add a MUBUF store pattern for Reg+Imm offsetsTom Stellard2014-02-061-1/+6
| | | | llvm-svn: 200935
* R600/SI: Add a MUBUF store pattern for Imm offsetsTom Stellard2014-02-061-0/+5
| | | | llvm-svn: 200934
* R600/SI: Add a MUBUF load pattern for Reg+Imm offsetsTom Stellard2014-02-061-0/+5
| | | | llvm-svn: 200933
* R600/SI: Use immediates offsets for SMRD instructions whenever possibleTom Stellard2014-02-061-3/+3
| | | | | | | | There was a problem with the old pattern, so we were copying some larger immediates into registers when we could have been encoding them in the instruction. llvm-svn: 200932
* R600/SI: Add pattern for zero-extending i1 to i32Michel Danzer2014-02-051-0/+5
| | | | | | | | | Fixes opencl-example if_* tests with radeonsi. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74469 Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 200830
* R600/SI: Fix fneg for 0.0Michel Danzer2014-02-041-4/+18
| | | | | | | | | | | | V_ADD_F32 with source modifier does not produce -0.0 for this. Just manipulate the sign bit directly instead. Also add a pattern for (fneg (fabs ...)). Fixes a bunch of bit encoding piglit tests with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 200743
* R600/SI: Fix insertelement with dynamic indices.Matt Arsenault2014-02-021-7/+17
| | | | | | | | This didn't work for any integer vectors, and didn't work with some sizes of float vectors. This should now work with all sizes of float and i32 vectors. llvm-svn: 200619
* R600/SI: Add pattern for truncating i32 to i1Michel Danzer2014-01-281-0/+5
| | | | | | | Fixes half a dozen piglit tests with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 200283
* R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructionsMichel Danzer2014-01-271-2/+46
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 200196
* R600/SI: Add intrinsic for S_SENDMSG instructionMichel Danzer2014-01-271-2/+14
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 200195
* R600/SI: Make private pointers be 32-bit.Matt Arsenault2013-12-191-3/+3
| | | | | | | | Different sized address spaces should theoretically work most of the time now, and since 64-bit add is currently disabled, using more 32-bit pointers fixes some cases. llvm-svn: 197659
* Fix typo in instruction name.Matt Arsenault2013-12-161-1/+1
| | | | | | SI_KIL -> SI_KILL llvm-svn: 197425
* R600/SI: Implement spilling of SGPRs v5Tom Stellard2013-11-271-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions. v2: - Fix encoding of Lane Mask - Use correct register flags, so we don't overwrite the low dword when restoring multi-dword registers. v3: - Register spilling seems to hang the GPU, so replace all shaders that need spilling with a dummy shader. v4: - Fix *LANE definitions - Change destination reg class for 32-bit SMRD instructions v5: - Remove small optimization that was crashing Serious Sam 3. https://bugs.freedesktop.org/show_bug.cgi?id=68224 https://bugs.freedesktop.org/show_bug.cgi?id=71285 NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195880
* R600/SI: Use SGPR_32 register class for 32-bit SMRD outputsTom Stellard2013-11-271-2/+5
| | | | | | | | Writing to the M0 register from an SMRD instruction hangs the GPU, so we need to use the SGPR_32 register class, which does not include M0. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195879
* R600/SI: Fixing handling of condition codesTom Stellard2013-11-221-39/+39
| | | | | | | | We were ignoring the ordered/onordered bits and also the signed/unsigned bits of condition codes when lowering the DAG to MachineInstrs. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195514
* R600/SI: Specify SSrc operandsMatt Arsenault2013-11-181-2/+2
| | | | llvm-svn: 195039
* R600/SI: Match addc to S_ADD_U32.Matt Arsenault2013-11-181-0/+7
| | | | | | The carry always goes to SCC. llvm-svn: 195037
* R600/SI: Match adde/sube to S_ADDC_U32/S_SUBB_U32Matt Arsenault2013-11-181-2/+4
| | | | llvm-svn: 195036
* R600/SI: Specify S_ADD/S_SUB set SCC and add is commutableMatt Arsenault2013-11-181-1/+13
| | | | llvm-svn: 195035
* R600/SI: Move patterns to match add / sub to scalar instructionsMatt Arsenault2013-11-181-10/+12
| | | | llvm-svn: 195034
* R600/SI: Specify S_ADDK/S_MULK set SCC and are commutableMatt Arsenault2013-11-141-2/+5
| | | | llvm-svn: 194738
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-1/+37
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-131-6/+29
| | | | | | | | | | | | | | All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. llvm-svn: 194625
* R600/SI: Add compute support for CI v2Tom Stellard2013-10-291-1/+1
| | | | | | | | v2: - Fix LDS size calculation Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 193621
* R600: Fix handling of vector kernel argumentsTom Stellard2013-10-231-0/+3
| | | | | | | | | | The SelectionDAGBuilder was promoting vector kernel arguments to legal types, but this won't work for R600 and SI since kernel arguments are stored in memory and can't be promoted. In order to handle vector arguments correctly we need to look at the original types from the LLVM IR function. llvm-svn: 193215
* R600/SI: Add support for i64 bitwise orTom Stellard2013-10-231-0/+19
| | | | llvm-svn: 193213
* R600/SI: Use S_LOAD_DWORD instructions for v8i32 and v16i32Tom Stellard2013-10-231-0/+3
| | | | llvm-svn: 193212
* Fix typoMatt Arsenault2013-10-151-1/+1
| | | | llvm-svn: 192752
* R600: improve dump of S_WAITCNTVincent Lejeune2013-10-131-1/+3
| | | | llvm-svn: 192557
* Fix typoMatt Arsenault2013-10-111-1/+1
| | | | llvm-svn: 192499
* R600: Fix trunc i64 to i32 on SIMatt Arsenault2013-10-101-0/+5
| | | | llvm-svn: 192375
* R600/SI: Define a separate MIMG instruction for each possible output value typeTom Stellard2013-10-101-25/+25
| | | | | | | | | | | | | During instruction selection, we rewrite the destination register class for MIMG instructions based on their writemasks. This creates machine verifier errors since the new register class does not match the register class in the MIMG instruction definition. We can avoid this by defining different MIMG instructions for each possible destination type and then switching to the correct instruction when we change the register class. llvm-svn: 192365
* R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedbackTom Stellard2013-09-121-4/+25
| | | | | | | | | | | | | For _XYZ, the type of VDATA is v4i32, because v3i32 doesn't exist. The ADDR64 bit is not exposed. A simpler intrinsic that doesn't take a resource descriptor might be nicer. The maximum number of input SGPRs is bumped to 17. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 190575
* R600: Add support for LDS atomic subtractAaron Watry2013-09-061-0/+4
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 190200
* R600: Add support for local memory atomic addTom Stellard2013-09-051-0/+4
| | | | llvm-svn: 190080
* R600: Add support for i8 and i16 local memory loadsTom Stellard2013-08-261-0/+14
| | | | llvm-svn: 189225
* R600: Add support for i8 and i16 local memory storesTom Stellard2013-08-261-3/+9
| | | | llvm-svn: 189223
* SelectionDAG: Use correct pointer size when lowering function arguments v2Tom Stellard2013-08-261-5/+4
| | | | | | | | | | | | | | | | This adds minimal support to the SelectionDAG for handling address spaces with different pointer sizes. The SelectionDAG should now correctly lower pointer function arguments to the correct size as well as generate the correct code when lowering getelementptr. This patch also updates the R600 DataLayout to use 32-bit pointers for the local address space. v2: - Add more helper functions to TargetLoweringBase - Use CHECK-LABEL for tests llvm-svn: 189221
* R600/SI: Add pattern for xor of i1Michel Danzer2013-08-161-1/+3
| | | | | | | Fixes two recent piglit regressions with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 188559
* Revert "R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions"Tom Stellard2013-08-161-3/+3
| | | | | | | This reverts commit a6a39ced095c2f453624ce62c4aead25db41a18f. This is the wrong version of this fix. llvm-svn: 188523
* R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructionsTom Stellard2013-08-161-3/+3
| | | | | | | | | The SIInsertWaits pass was overwriting the first operand (gds bit) of DS_WRITE_B32 with the second operand (value to write). This meant that any time the value to write was stored in an odd number VGPR, the gds bit would be set causing the instruction to write to GDS instead of LDS. llvm-svn: 188522
* R600: Add support for i16 and i8 global storesTom Stellard2013-08-161-12/+20
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188519
* R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsicsTom Stellard2013-08-141-1/+1
| | | | llvm-svn: 188430
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