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path: root/llvm/lib/Target/R600/SIInstructions.td
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* R600/SI: Fix selection failure on scalar_to_vectorMatt Arsenault2014-06-111-1/+2
| | | | | | | | | | | There seem to be only 2 places that produce these, and it's kind of tricky to hit them. Also fixes failure to bitcast between i64 and v2f32, although this for some reason wasn't actually broken in the simple bitcast testcase, but did in the scalar_to_vector one. llvm-svn: 210664
* R600/SI: Fix a crash when spilling SGPRsTom Stellard2014-06-101-0/+1
| | | | | | | | | | | We need to make sure only one new instruction is added when spilling otherwise the register allocator may crash. This fixes a crash in the game Antichamber. https://bugs.freedesktop.org/show_bug.cgi?id=75276 llvm-svn: 210587
* R600/SI: Implement i64 ctpopMatt Arsenault2014-06-101-1/+9
| | | | llvm-svn: 210568
* R600/SI: Use bcnt instruction for ctpopMatt Arsenault2014-06-101-2/+9
| | | | llvm-svn: 210567
* R600: Handle fcopysignMatt Arsenault2014-06-101-1/+1
| | | | llvm-svn: 210564
* R600/SI: Handle sign_extend and zero_extend to i64 with patterns.Matt Arsenault2014-06-101-0/+36
| | | | llvm-svn: 210563
* R600/SI: Rename VOP3 helper class to be more generalMatt Arsenault2014-06-091-3/+3
| | | | | | It has other uses besides shift instructions. llvm-svn: 210478
* R600/SI: Keep 64-bit not on SALUMatt Arsenault2014-06-091-1/+3
| | | | llvm-svn: 210476
* R600/SI: Match rsq instructionsMatt Arsenault2014-06-051-2/+6
| | | | llvm-svn: 210226
* R600/SI: Remove redundant patternsMatt Arsenault2014-05-311-14/+0
| | | | | | These patterns are already handled in the instruction definition. llvm-svn: 209979
* R600/SI: Fix [s|u]int_to_fp for i1Matt Arsenault2014-05-311-0/+20
| | | | llvm-svn: 209971
* R600/SI: Fix pattern variable names.Matt Arsenault2014-05-291-2/+2
| | | | | | | These are confusing enough since the order swaps, so give them more useful names. llvm-svn: 209787
* R600: Add intrinsics for mad24Matt Arsenault2014-05-221-2/+6
| | | | llvm-svn: 209456
* R600/SI: Move instruction pattern to instruction definitionMatt Arsenault2014-05-221-6/+3
| | | | llvm-svn: 209454
* R600/SI: Match fp_to_uint / uint_to_fp for f64Matt Arsenault2014-05-221-2/+7
| | | | llvm-svn: 209388
* R600/SI: Refactor the VOP3_32 tablegen classTom Stellard2014-05-161-26/+26
| | | | | | | | This will allow us to use a single MachineInstr to represent instructions which behave the same but have different encodings on some subtargets. llvm-svn: 209028
* R600/SI: Add a PredicateControl class for managing TableGen predicatesTom Stellard2014-05-161-27/+10
| | | | | | This was inspired by the PredicateControl class in the MIPS backend. llvm-svn: 209027
* R600/SI: Move tablegen patterns away from instruction defsTom Stellard2014-05-161-30/+31
| | | | llvm-svn: 209026
* R600/SI: Remove unused instructionTom Stellard2014-05-161-7/+0
| | | | llvm-svn: 209025
* R600/SI: Promote f32 SELECT to i32Tom Stellard2014-05-161-6/+0
| | | | llvm-svn: 209024
* R600/SI: Remove duplicate patternTom Stellard2014-05-161-5/+0
| | | | llvm-svn: 209023
* R600/SI: Stop using VSrc_* as the default register class for types.Tom Stellard2014-05-151-21/+4
| | | | | | | | | | We now use SReg_* for integer types and VReg_* for floating-point types. This should help simplify the SIFixSGPRCopies pass and no longer causes ISel to insert a COPY after termiator instuctions that output a value. This change is covered by exisitng tests. llvm-svn: 208888
* R600/SI: Use VALU instructions for i1 opsTom Stellard2014-05-151-10/+10
| | | | llvm-svn: 208885
* R600/SI: Prettier display of input modifiersVincent Lejeune2014-05-101-2/+6
| | | | llvm-svn: 208479
* R600/SI: Use pseudo instruction for fabs/clamp/fnegVincent Lejeune2014-05-101-4/+30
| | | | llvm-svn: 208478
* R600/SI: Fix SMRD pattern for offsets > 32 bitsTom Stellard2014-05-091-2/+2
| | | | | | We were dropping the high bits of 64-bit immediate offsets. llvm-svn: 208431
* R600/SI: Only create one instruction when spilling/restoring register v3Tom Stellard2014-05-021-1/+22
| | | | | | | | | | | | | | | | | | The register spiller assumes that only one new instruction is created when spilling and restoring registers, so we need to emit pseudo instructions for vector register spills and lower them after register allocation. v2: - Fix calculation of lane index - Extend VGPR liveness to end of program. v3: - Use SIMM16 field of S_NOP to specify multiple NOPs. https://bugs.freedesktop.org/show_bug.cgi?id=75005 llvm-svn: 207843
* R600/SI: Use VALU instructions for copying i1 valuesTom Stellard2014-04-301-5/+6
| | | | | | | | | We can't use SALU instructions for this since they ignore the EXEC mask and are always executed. This fixes several OpenCV tests. llvm-svn: 207661
* R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errorsTom Stellard2014-04-291-6/+23
| | | | | | | | | | | | | | | | SI_IF and SI_ELSE are terminators which also produce a value. For these instructions ISel always inserts a COPY to move their value to another basic block. This COPY ends up between SI_(IF|ELSE) and the S_BRANCH* instruction at the end of the block. This breaks MachineBasicBlock::getFirstTerminator() and also the machine verifier which assumes that terminators are grouped together at the end of blocks. To solve this we coalesce the copy away right after ISel to make sure there are no instructions in between terminators at the end of blocks. llvm-svn: 207591
* R600/SI: Only select SALU instructions in the entry or exit blockTom Stellard2014-04-291-27/+102
| | | | | | | | SALU instructions ignore control flow, so it is not always safe to use them within branches. This is a partial solution to this problem until we can come up with something better. llvm-svn: 207590
* R600/SI: Reorganize SIInstructions.tdTom Stellard2014-04-221-312/+381
| | | | llvm-svn: 206902
* R600: Make sign_extend_inreg legal.Matt Arsenault2014-04-221-15/+34
| | | | | | Don't know why I didn't just do this in the first place. llvm-svn: 206862
* R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16Matt Arsenault2014-04-181-2/+21
| | | | llvm-svn: 206547
* R600/SI: Stop using i128 as the resource descriptor typeTom Stellard2014-04-171-25/+15
| | | | | | | | | Having i128 as a legal type complicates the legalization phase. v4i32 is already a legal type, so we will use that instead. This fixes several piglit tests. llvm-svn: 206500
* R600/SI: f64 frint is legal on CIMatt Arsenault2014-04-171-2/+3
| | | | llvm-svn: 206475
* R600/SI: Refactor SOPC classes slightly.Matt Arsenault2014-04-111-12/+12
| | | | | | | Better match what is done for VOPC to eventually prefer selecting these. llvm-svn: 206048
* R600/SI: Match not instruction.Matt Arsenault2014-04-091-1/+4
| | | | llvm-svn: 205837
* R600: Match 24-bit arithmetic patterns in a Target DAGCombineTom Stellard2014-04-071-4/+4
| | | | | | | | | | | | | | | | | Moving these patterns from TableGen files to PerformDAGCombine() should allow us to generate better code by eliminating unnecessary shifts and extensions earlier. This also fixes a bug where the MAD pattern was calling SimplifyDemandedBits with a 24-bit mask on the first operand even when the full pattern wasn't being matched. This occasionally resulted in some instructions being incorrectly deleted from the program. v2: - Fix bug with 64-bit mul llvm-svn: 205731
* R600/SI: Lower 64-bit immediates using REG_SEQUENCETom Stellard2014-04-031-15/+0
| | | | llvm-svn: 205561
* R600/SI: Remove leftover pattern splitting 64-bit ors.Matt Arsenault2014-03-311-8/+0
| | | | | | | It's now matched to the scalar 64-bit or and split later if necessary.' llvm-svn: 205252
* R600: Add target nodes for BFM and BFIMatt Arsenault2014-03-311-2/+4
| | | | llvm-svn: 205235
* R600/SI: Lower i64 SELECT by bitcasting to a vector typeTom Stellard2014-03-311-0/+1
| | | | | | | This allows allows us to replace ISD::EXTRACT_ELEMENT, which is lowered using shifts, with ISD::EXTRACT_VECTOR_ELT, which is a no-op. llvm-svn: 205187
* R600/SI: Fix 64-bit bit ops that require the VALU.Matt Arsenault2014-03-241-1/+1
| | | | | | | | Try to match scalar and first like the other instructions. Expand 64-bit ands to a pair of 32-bit ands since that is not available on the VALU. llvm-svn: 204660
* R600/SI: Promote fp64 SELECT to i64Tom Stellard2014-03-241-12/+0
| | | | | | | This type promotion is replacing a Tablegen pattern and it is already covered by existing tests. llvm-svn: 204617
* R600/SI: Move instruction patterns to scalar versions.Matt Arsenault2014-03-211-38/+38
| | | | | | | Some of them also had the pattern on both, so this removes the duplication. llvm-svn: 204492
* R600/SI: Add unused LDS 2 form instructions.Matt Arsenault2014-03-191-0/+11
| | | | llvm-svn: 204275
* R600/SI: Add support for 64-bit LDS writesMatt Arsenault2014-03-191-1/+4
| | | | llvm-svn: 204274
* R600/SI: Add support for 64-bit LDS loads.Matt Arsenault2014-03-191-0/+2
| | | | | | | v2: -Use correct opcode for DS_READ_64 llvm-svn: 204273
* R600/SI: Match i16 immediate offset of LDS instructions.Matt Arsenault2014-03-191-20/+30
| | | | llvm-svn: 204272
* R600/SI: Merge offset0 and offset1 fields for single address DS instructions v2Matt Arsenault2014-03-191-5/+5
| | | | | | | | | Also remove unused data fields from the DS_Load_Helper class. v2: - Merge fields for DS_WRITE llvm-svn: 204269
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