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* R600/SI: Change all instruction assembly names to lowercase.Tom Stellard2014-11-051-856/+856
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matches the format produced by the AMD proprietary driver. //==================================================================// // Shell script for converting .ll test cases: (Pass the .ll files you want to convert to this script as arguments). //==================================================================// ; This was necessary on my system so that A-Z in sed would match only ; upper case. I'm not sure why. export LC_ALL='C' TEST_FILES="$*" MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r` for f in $TEST_FILES; do # Check that there are SI tests: grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f if [ $? -eq 0 ]; then for match in $MATCHES; do sed -i -e "s/\([ :]$match\)/\L\1/" $f done # Try to get check lines with partial instruction names sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f fi done sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll //==================================================================// // Shell script for converting .td files (run this last) //==================================================================// export LC_ALL='C' sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td llvm-svn: 221350
* R600/SI: Use REG_SEQUENCE instead of INSERT_SUBREGsMatt Arsenault2014-11-021-41/+35
| | | | llvm-svn: 221118
* Support REG_SEQUENCE in tablegen.Matt Arsenault2014-11-021-3/+3
| | | | | | | | | The problem is mostly that variadic output instruction aren't handled, so it is rejected for having an inconsistent number of operands, and then the right number of operands isn't emitted. llvm-svn: 221117
* Add minnum / maxnum codegenMatt Arsenault2014-10-211-4/+5
| | | | llvm-svn: 220342
* R600/SI: Add pattern for bswapMatt Arsenault2014-10-211-0/+7
| | | | llvm-svn: 220304
* R600/SI: Add global atomicrmw xchgAaron Watry2014-10-171-0/+3
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220110
* R600/SI: Add global atomicrmw xorAaron Watry2014-10-171-1/+3
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220109
* R600/SI: Add global atomicrmw orAaron Watry2014-10-171-1/+3
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220108
* R600/SI: Add global atomicrmw min/uminAaron Watry2014-10-171-2/+6
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220107
* R600/SI: Add global atomicrmw max/umaxAaron Watry2014-10-171-2/+6
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220106
* R600/SI: Add global atomicrmw andAaron Watry2014-10-171-1/+3
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220105
* R600/SI: Add global atomicrmw subAaron Watry2014-10-171-1/+3
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220104
* R600/SI: Remove redundant setting of instruction bitsMatt Arsenault2014-10-171-4/+0
| | | | | | These are all set on the instruction base classes. llvm-svn: 220091
* R600/SI: Use complex pattern for MUBUF load patterns.Matt Arsenault2014-10-171-3/+2
| | | | | | This eliminates a use of the SI_ADDR64_RSRC pseudo llvm-svn: 220057
* R600/SI: Remove SI_BUFFER_RSRC pseudoMatt Arsenault2014-10-171-6/+0
| | | | | | | Just use REG_SEQUENCE directly, so there are fewer instructions to need to deal with later. llvm-svn: 220056
* R600/SI: Remove another VALU patternMatt Arsenault2014-10-161-5/+0
| | | | llvm-svn: 219988
* R600/SI: Remove unnecessary VALU patternsMatt Arsenault2014-10-161-41/+0
| | | | | | | | These haven't been necessary since allowing selecting SALU instructions in non-entry blocks was enabled. llvm-svn: 219956
* R600/SI: Refactor VOP3 instruction defsTom Stellard2014-10-071-47/+47
| | | | llvm-svn: 219256
* R600/SI: Refactor VOPC instruction defsTom Stellard2014-10-071-196/+196
| | | | llvm-svn: 219255
* R600/SI: Refactor VOP2 instruction defsTom Stellard2014-10-071-35/+34
| | | | llvm-svn: 219254
* R600/SI: Refactor VOP1 instruction defsTom Stellard2014-10-071-57/+56
| | | | llvm-svn: 219253
* R600/SI: Add a generic pseudo EXP instructionTom Stellard2014-10-011-0/+6
| | | | llvm-svn: 218767
* R600/SI: Add generic pseudo MTBUF instructionsTom Stellard2014-10-011-5/+5
| | | | llvm-svn: 218766
* R600/SI: Add support for global atomic addTom Stellard2014-09-251-1/+3
| | | | llvm-svn: 218457
* R600/SI: Enable selecting SALU inside branchesTom Stellard2014-09-241-9/+0
| | | | | | We can do this now that the FixSGPRLiveRanges pass is working. llvm-svn: 218353
* R600/SI: Fix the FixSGPRLiveRanges passTom Stellard2014-09-241-0/+4
| | | | | | | | | | | The previous implementation was extending the live range of SGPRs by modifying the live intervals directly. This was causing a lot of machine verification errors when the machine scheduler was enabled. The new implementation adds pseudo instructions with implicit uses to extend the live ranges of SGPRs, which works much better. llvm-svn: 218351
* R600/SI: Implement VGPR register spilling for compute at -O0 v3Tom Stellard2014-09-241-0/+21
| | | | | | | | | | | | | | VGPRs are spilled to LDS. This still needs more testing, but we need to at least enable it at -O0, because the fast register allocator spills all registers that are live at the end of blocks and without this some future commits will break the flat-address-space.ll test. v2: Only calculate thread id once v3: Move insertion of spill instructions to SIRegisterInfo::eliminateFrameIndex() llvm-svn: 218348
* Revert "R600/SI: Add support for global atomic add"Tom Stellard2014-09-221-3/+1
| | | | | | | | | This reverts commit r218254. The global_atomics.ll test fails with asserts disabled. For some reason, the compiler fails to produce the atomic no return variants. llvm-svn: 218257
* R600/SI: Add support for global atomic addTom Stellard2014-09-221-1/+3
| | | | llvm-svn: 218254
* R600/SI: Remove modifier operands from V_CNDMASK_B32_e64Tom Stellard2014-09-221-3/+2
| | | | | | Modifiers don't work for this instruction. llvm-svn: 218253
* R600/SI: Prefer selecting more e64 instruction forms.Matt Arsenault2014-09-151-7/+7
| | | | | | | | Add some more tests to make sure better operand choices are still made. Leave some cases that seem to have no reason to ever be e64 alone. llvm-svn: 217789
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-151-0/+106
| | | | llvm-svn: 217777
* R600/SI: Replace LDS atomics with no return versionsMatt Arsenault2014-09-081-1/+1
| | | | llvm-svn: 217379
* R600/SI: Add InstrMapping for noret atomics.Matt Arsenault2014-09-081-41/+41
| | | | | | | | Only handles LDS atomics for now, and will be used to replace atomics with no uses with the no return versions. llvm-svn: 217378
* R600/SI: Fix register class for some 64-bit atomicsMatt Arsenault2014-09-071-5/+5
| | | | llvm-svn: 217323
* R600/SI: Use same complex patterns for DS atomicsMatt Arsenault2014-09-051-67/+47
| | | | | | | This fixes hitting the same negative base offset problem that was already fixed for regular loads and stores. llvm-svn: 217256
* R600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of 64-bit operationsTom Stellard2014-09-051-2/+2
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=83416 llvm-svn: 217248
* R600/SI: Un-move pattern I forgot to remove in last commitMatt Arsenault2014-09-031-5/+5
| | | | llvm-svn: 217109
* R600/SI: Try to keep i32 mul on SALUMatt Arsenault2014-09-031-7/+11
| | | | | | | Also fix bug this exposed where when legalizing an immediate operand, a v_mov_b32 would be created with a VSrc dest register. llvm-svn: 217108
* R600/SI: Add a pattern for i64 and in a branchTom Stellard2014-09-031-0/+1
| | | | llvm-svn: 217041
* R600/SI: Use mad for fsub + fmulMatt Arsenault2014-08-291-0/+3
| | | | | | | We can use a negate source modifier to match this for fsub. llvm-svn: 216735
* R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops with 32-bit alignmentTom Stellard2014-08-221-2/+24
| | | | llvm-svn: 216279
* R600/SI: Use a ComplexPattern for DS loads and storesTom Stellard2014-08-221-32/+18
| | | | llvm-svn: 216278
* R600/SI: Use eliminateFrameIndex() to expand SGPR spill pseudosTom Stellard2014-08-211-2/+2
| | | | | | | | | | | | | | | This will simplify the SGPR spilling and also allow us to use MachineFrameInfo for calculating offsets, which should be more reliable than our custom code. This fixes a crash in some cases where a register would be spilled in a branch such that the VGPR defined for spilling did not dominate all the uses when restoring. This fixes a crash in an ocl conformance test. The test requries register spilling and is too big to include. llvm-svn: 216217
* R600/SI: Move all fabs / fneg handling to patternsMatt Arsenault2014-08-151-28/+31
| | | | llvm-svn: 215749
* R600/SI: Use source modifiers for f64 fnegMatt Arsenault2014-08-151-1/+9
| | | | llvm-svn: 215748
* R600/SI: Refactor fneg / fabs patternsMatt Arsenault2014-08-151-22/+17
| | | | llvm-svn: 215746
* R600/SI: Add intrinsic for ldexpMatt Arsenault2014-08-151-2/+2
| | | | llvm-svn: 215734
* R600/SI: Add an _OFFEN variant MUBUF_STORE_* and use it for scratch writesTom Stellard2014-08-111-12/+10
| | | | llvm-svn: 215398
* R600/SI: Add definitions for ds_read2st64_ / ds_write2st64_Matt Arsenault2014-08-051-3/+4
| | | | llvm-svn: 214936
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