summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/R600/SIInstrInfo.td
Commit message (Collapse)AuthorAgeFilesLines
...
* R600/SI: Refactor SOP1 classesTom Stellard2015-02-131-26/+19
| | | | llvm-svn: 229152
* R600/SI: Remove some unused TableGen classesTom Stellard2015-02-131-19/+0
| | | | llvm-svn: 229150
* R600/SI: Add soffset operand to mubuf addr64 instructionTom Stellard2015-02-111-16/+20
| | | | | | We were previously hard-coding soffset to 0. llvm-svn: 228775
* R600/SI: Also enable WQM for image opcodes which calculate LOD v3Michel Danzer2015-02-061-22/+38
| | | | | | | | | | | | | If whole quad mode isn't enabled for these, the level of detail is calculated incorrectly for pixels along diagonal triangle edges, causing artifacts. v2: Use a TSFlag instead of lots of switch cases v3: Add test coverage Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88642 Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 228372
* R600/SI: Rewrite VOP1InstSI to contain a pseudo and _si opcodeMarek Olsak2015-02-031-7/+23
| | | | | | | | | | | What this does is that if you accidentally select these instructions on VI, the code generation will fail, because the pseudo -> _vi mapping will be undefined. The idea is to be able to catch possible future bugs easily. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 228038
* R600/SI: Fix B64 VALU shifts on VIMarek Olsak2015-02-031-0/+1
| | | | | | | SI only has standard versions. VI only has REV versions. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 228037
* R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VIMarek Olsak2015-02-031-4/+30
| | | | | | | | | | | | | | | This can happen when a REV instruction is commuted. The trick is not to define the _vi versions of instructions, which has these consequences: - code generation will always fail if a pseudo cannot be lowered (very useful to catch bugs where an unsupported instruction somehow makes it to the printer) - ability to query if a pseudo can be lowered, which is done in commuteOpcode to prevent REV from commuting to non-REV on VI Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 227990
* R600/SI: Remove VOP2_REV definitions from target-specific instructionsMarek Olsak2015-02-031-26/+19
| | | | | | | | | | | The getCommute* functions are only used with pseudos, so this commit doesn't change anything. The issue with missing non-rev versions of shift instructions on VI will fixed separately. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 227989
* R600/SI: Trivial instruction definition corrections for VI (v2)Marek Olsak2015-02-031-0/+1
| | | | | | | | | | | | - V_MAC_LEGACY_F32 exists on VI, but it's VOP3-only. - Define CVT_PK opcodes which are different between SI and VI. These are unused. The idea is to define all chip differences. v2: keep V_MUL_LO_U32 Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 227988
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-301-3/+2
| | | | | | without a Function argument. llvm-svn: 227638
* R600/SI: Don't set patterns for chip-specific instructions while having pseudosMarek Olsak2015-01-271-50/+43
| | | | | | | | | | | Only pseudos have patterns on them. Also don't set the asm string for VINTRP_Pseudo. All pseudos should have empty asm. This matches what all other multiclasses do. llvm-svn: 227212
* R600/SI: Add VI versions of LDS atomicsMarek Olsak2015-01-271-44/+66
| | | | | | | Each class is split into two: one adds let statements around non-pseudos, and the other one specifies the parameters. llvm-svn: 227211
* R600/SI: Add VI versions of MUBUF atomicsMarek Olsak2015-01-271-31/+42
| | | | llvm-svn: 227210
* R600/SI: Add VI versions of MUBUF loads and storesMarek Olsak2015-01-271-55/+15
| | | | | | This enables a lot of existing patterns for VI. llvm-svn: 227209
* R600/SI: Add pseudos for MUBUF loads and storesMarek Olsak2015-01-271-103/+125
| | | | | | | | | This defines the SI versions only, so it shouldn't change anything. There are no changes other than using the new multiclasses, adding missing mayLoad/mayStore, and formatting fixes. llvm-svn: 227208
* R600/SI: Fix trailing comma with modifiersMatt Arsenault2015-01-151-1/+1
| | | | | | | Instructions with 1 operand can still use source modifiers, so make sure we don't print an extra comma afterwards. llvm-svn: 226226
* R600/SI: Unify VOP2 instructions which are VOP3-only on VIMarek Olsak2015-01-151-38/+43
| | | | | | | | | | | | | This removes some duplicated classes and definitions. These instructions are defined: _e32 // pseudo _e32_si _e64 // pseudo _e64_si _e64_vi llvm-svn: 226191
* R600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VIMarek Olsak2015-01-151-0/+17
| | | | | | | | These are VOP3-only on VI. The new multiclass doesn't define VOP3 versions of VOP2 instructions. llvm-svn: 226189
* R600/SI: Don't shrink instructions whose e32 encoding doesn't existMarek Olsak2015-01-151-1/+1
| | | | | | | | v2: modify hasVALU32BitEncoding instead v3: - add pseudoToMCOpcode helper to AMDGPUInstInfo, which is used by both hasVALU32BitEncoding and AMDGPUMCInstLower::lower - report an error if a pseudo can't be lowered llvm-svn: 226188
* R600/SI: Spill VGPRs to scratch space for compute shadersTom Stellard2015-01-141-0/+2
| | | | llvm-svn: 225988
* R600/SI: Add pattern for bitcasting fp immediates to integersTom Stellard2015-01-131-0/+12
| | | | | | | | The backend now assumes that all immediates are integers. This allows us to simplify immediate handling code, becasue we no longer need to handle fp and integer immediates differently. llvm-svn: 225844
* R600/SI: Use RegisterOperands to specify which operands can accept immediatesTom Stellard2015-01-121-13/+13
| | | | | | | | | | | | There are some operands which can take either immediates or registers and we were previously using different register class to distinguish between operands that could take immediates and those that could not. This patch switches to using RegisterOperands which should simplify the backend by reducing the number of register classes and also make it easier to implement the assembler. llvm-svn: 225662
* R600/SI: Remove VReg_32 register classTom Stellard2015-01-071-26/+26
| | | | | | | | | | | Use VGPR_32 register class instead. These two register classes were identical and having separate classes was causing SIInstrInfo::isLegalOperands() to be overly conservative in some cases. This change is necessary to prevent future paches from missing a folding opportunity in fneg-fabs.ll. llvm-svn: 225382
* R600/SI: Add class intrinsicMatt Arsenault2015-01-061-1/+40
| | | | llvm-svn: 225305
* R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operandTom Stellard2014-12-191-15/+15
| | | | | | | | mubuf instructions now define the soffset field using the SCSrc_32 register class which indicates that only SGPRs and inline constants are allowed. llvm-svn: 224622
* R600/SI: Fix f64 inline immediatesMatt Arsenault2014-12-171-0/+4
| | | | llvm-svn: 224458
* R600/SI: Set MayStore = 0 on MUBUF loadsTom Stellard2014-12-091-1/+1
| | | | llvm-svn: 223722
* R600/SI: Move setting of the lds bit to the base MUBUF classTom Stellard2014-12-091-6/+9
| | | | llvm-svn: 223721
* R600/SI: Set 20-bit immediate byte offset for SMRD on VIMarek Olsak2014-12-071-0/+4
| | | | llvm-svn: 223614
* R600/SI: Add VI instructionsMarek Olsak2014-12-071-121/+579
| | | | llvm-svn: 223603
* R600/SI: Remove i1 pseudo VALU opsMatt Arsenault2014-12-031-0/+4
| | | | | | | | | | | | | | Select i1 logical ops directly to 64-bit SALU instructions. Vector i1 values are always really in SGPRs, with each bit for each item in the wave. This saves about 4 instructions when and/or/xoring any condition, and also helps write conditions that need to be passed in vcc. This should work correctly now that the SGPR live range fixing pass works. More work is needed to eliminate the VReg_1 pseudo regclass and possibly the entire SILowerI1Copies pass. llvm-svn: 223206
* R600/SI: Various instruction format bit test cleanupsMatt Arsenault2014-12-011-8/+0
| | | | | | | | | | | - Fix missing SALU format bits - Remove unused isSALUInstr - Add isVALU - Switch isDS to use a bit like the others - Move SIInstrInfo::is* functions to header - Reorder so they are approximately sorted by type (SALU, VALU, memory) llvm-svn: 223038
* R600/SI: Emit s_mov_b32 m0, -1 before every DS instructionTom Stellard2014-11-211-8/+9
| | | | | | | | | | | | This s_mov_b32 will write to a virtual register from the M0Reg class and all the ds instructions now take an extra M0Reg explicit argument. This change is necessary to prevent issues with the scheduler mixing together instructions that expect different values in the m0 registers. llvm-svn: 222583
* R600/SI: Set hasSideEffects = 0 on load and store instructions.Matt Arsenault2014-11-181-1/+4
| | | | | | | | | | Assuming unmodeled side effects interferes with some scheduling opportunities. Don't put it in the base class of DS instructions since there are a few weird effecting, non load/store instructions there. llvm-svn: 222285
* R600/SI: Use S_BFE_I64 for 64-bit sext_inregMatt Arsenault2014-11-141-0/+5
| | | | llvm-svn: 222012
* R600/SI: Use s_movk_i32Matt Arsenault2014-11-131-2/+2
| | | | llvm-svn: 221922
* R600/SI: Fix definition for s_cselect_b32Matt Arsenault2014-11-131-0/+5
| | | | | | | | | | | These were directly using the old base instruction class, and specifying the wrong register classes for operands. The operands can be the other special inputs besides SGPRs. The op name was also being directly used for the asm string, so this was printed without any operands. llvm-svn: 221921
* R600/SI: Get rid of FCLAMP_SI pseudoMatt Arsenault2014-11-131-0/+1
| | | | | | | It's not necessary. Also use complex patterns to allow src modifier usage. llvm-svn: 221916
* R600/SI: Fix omod display for VOP3bMatt Arsenault2014-11-051-1/+1
| | | | llvm-svn: 221387
* R600/SI: Change all instruction assembly names to lowercase.Tom Stellard2014-11-051-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matches the format produced by the AMD proprietary driver. //==================================================================// // Shell script for converting .ll test cases: (Pass the .ll files you want to convert to this script as arguments). //==================================================================// ; This was necessary on my system so that A-Z in sed would match only ; upper case. I'm not sure why. export LC_ALL='C' TEST_FILES="$*" MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r` for f in $TEST_FILES; do # Check that there are SI tests: grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f if [ $? -eq 0 ]; then for match in $MATCHES; do sed -i -e "s/\([ :]$match\)/\L\1/" $f done # Try to get check lines with partial instruction names sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f fi done sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll //==================================================================// // Shell script for converting .td files (run this last) //==================================================================// export LC_ALL='C' sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td llvm-svn: 221350
* R600/SI: Rename div_scale dest operands to match documentationMatt Arsenault2014-11-041-2/+2
| | | | llvm-svn: 221291
* R600/SI: Change how DS offsets are printedMatt Arsenault2014-10-101-16/+25
| | | | | | | Match SC by using offset/offset0/offset1 and printing in decimal. llvm-svn: 219537
* R600/SI: Refactor VOP3 instruction defsTom Stellard2014-10-071-14/+17
| | | | llvm-svn: 219256
* R600/SI: Refactor VOPC instruction defsTom Stellard2014-10-071-17/+21
| | | | llvm-svn: 219255
* R600/SI: Refactor VOP2 instruction defsTom Stellard2014-10-071-7/+12
| | | | llvm-svn: 219254
* R600/SI: Refactor VOP1 instruction defsTom Stellard2014-10-071-7/+29
| | | | llvm-svn: 219253
* R600/SI: Add a generic pseudo EXP instructionTom Stellard2014-10-011-0/+24
| | | | llvm-svn: 218767
* R600/SI: Add generic pseudo MTBUF instructionsTom Stellard2014-10-011-24/+51
| | | | llvm-svn: 218766
* R600/SI: Add generic pseudo SMRD instructionsTom Stellard2014-10-011-12/+37
| | | | llvm-svn: 218765
* R600/SI: Fix printing of clamp and omodMatt Arsenault2014-09-301-17/+27
| | | | | | | | No tests for omod since nothing uses it yet, but this should get rid of the remaining annoying trailing zeros after some instructions. llvm-svn: 218692
OpenPOWER on IntegriCloud