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* R600/SI: Add unused LDS 2 form instructions.Matt Arsenault2014-03-191-1/+24
| | | | llvm-svn: 204275
* R600/SI: Match i16 immediate offset of LDS instructions.Matt Arsenault2014-03-191-0/+9
| | | | llvm-svn: 204272
* R600/SI: Don't display the GDS bit.Matt Arsenault2014-03-191-3/+3
| | | | | | | | It isn't actually used now, and probably never will be, plus it makes tests less annoying. I also think SC prints GDS instructions as a separate instruction name. llvm-svn: 204270
* R600/SI: Merge offset0 and offset1 fields for single address DS instructions v2Matt Arsenault2014-03-191-13/+22
| | | | | | | | | Also remove unused data fields from the DS_Load_Helper class. v2: - Merge fields for DS_WRITE llvm-svn: 204269
* R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCCTom Stellard2014-03-071-2/+2
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 203281
* R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are usedTom Stellard2014-02-101-0/+8
| | | | | | | | | | | DS instructions that access local memory can only uses addresses that are less than or equal to the value of M0. When M0 is uninitialized, then we experience undefined behavior. This patch also changes the behavior to emit S_WQM_B64 on pixel shaders no matter what kind of DS instruction is used. llvm-svn: 201097
* R600/SI: Add a MUBUF store pattern for Reg+Imm offsetsTom Stellard2014-02-061-0/+5
| | | | llvm-svn: 200935
* R600/SI: Use immediates offsets for SMRD instructions whenever possibleTom Stellard2014-02-061-7/+10
| | | | | | | | There was a problem with the old pattern, so we were copying some larger immediates into registers when we could have been encoding them in the instruction. llvm-svn: 200932
* R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructionsMichel Danzer2014-01-271-19/+41
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 200196
* R600/SI: Make private pointers be 32-bit.Matt Arsenault2013-12-191-1/+1
| | | | | | | | Different sized address spaces should theoretically work most of the time now, and since 64-bit add is currently disabled, using more 32-bit pointers fixes some cases. llvm-svn: 197659
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-0/+4
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-131-0/+5
| | | | | | | | | | | | | | All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. llvm-svn: 194625
* R600/SI: Define a separate MIMG instruction for each possible output value typeTom Stellard2013-10-101-10/+51
| | | | | | | | | | | | | During instruction selection, we rewrite the destination register class for MIMG instructions based on their writemasks. This creates machine verifier errors since the new register class does not match the register class in the MIMG instruction definition. We can avoid this by defining different MIMG instructions for each possible destination type and then switching to the correct instruction when we change the register class. llvm-svn: 192365
* R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedbackTom Stellard2013-09-121-0/+27
| | | | | | | | | | | | | For _XYZ, the type of VDATA is v4i32, because v3i32 doesn't exist. The ADDR64 bit is not exposed. A simpler intrinsic that doesn't take a resource descriptor might be nicer. The maximum number of input SGPRs is bumped to 17. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 190575
* R600: Add support for local memory atomic addTom Stellard2013-09-051-0/+12
| | | | llvm-svn: 190080
* Revert "R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions"Tom Stellard2013-08-161-4/+4
| | | | | | | This reverts commit a6a39ced095c2f453624ce62c4aead25db41a18f. This is the wrong version of this fix. llvm-svn: 188523
* R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructionsTom Stellard2013-08-161-4/+4
| | | | | | | | | The SIInsertWaits pass was overwriting the first operand (gds bit) of DS_WRITE_B32 with the second operand (value to write). This meant that any time the value to write was stored in an odd number VGPR, the gds bit would be set causing the instruction to write to GDS instead of LDS. llvm-svn: 188522
* R600: Add support for i16 and i8 global storesTom Stellard2013-08-161-3/+3
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188519
* R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsicsTom Stellard2013-08-141-1/+1
| | | | llvm-svn: 188430
* R600/SI: Convert v16i8 resource descriptors to i128Tom Stellard2013-08-141-0/+20
| | | | | | | | | | | | | Now that compute support is better on SI, we can't continue using v16i8 for descriptors since this is also a legal type in OpenCL. This patch fixes numerous hangs with the piglit OpenCL test and since we now use a target specific DAG node for LOAD_CONSTANT with the correct MemOperandFlags, this should also fix: https://bugs.freedesktop.org/show_bug.cgi?id=66805 llvm-svn: 188429
* R600/SI: Choose the correct MOV instruction for copying immediatesTom Stellard2013-08-141-0/+16
| | | | | | | | The instruction selector will now try to infer the destination register so it can decided whether to use V_MOV_B32 or S_MOV_B32 when copying immediates. llvm-svn: 188426
* R600/SI: Assign a register class to the $vaddr operand for MIMG instructionsTom Stellard2013-08-141-13/+20
| | | | | | | The previous code declared the operand as unknown:$vaddr, which made it possible for scalar registers to be used instead of vector registers. llvm-svn: 188425
* R600/SI: Implement sint<->fp64 conversionsNiels Ole Salscheider2013-08-081-0/+6
| | | | llvm-svn: 187987
* R600: Remove unsafe type punning. No intended functionality change.Benjamin Kramer2013-07-121-6/+4
| | | | llvm-svn: 186196
* R600/SI: SI support for 64bit ConstantFPTom Stellard2013-07-121-0/+12
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186178
* R600/SI: Initial support for LDS/GDS instructionsMichel Danzer2013-07-101-0/+23
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186009
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-1/+2
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184360
* Cast to the correct type. Pointer, not reference.Bill Wendling2013-06-061-1/+1
| | | | llvm-svn: 183385
* R600/SI: Add support for global loadsTom Stellard2013-06-031-3/+6
| | | | llvm-svn: 183131
* R600/SI: Rework MUBUF store instructionsTom Stellard2013-06-031-9/+3
| | | | | | | The lowering of stores is now mostly handled in the tablegen files. No more BUFFER_STORE nodes I generated during legalization. llvm-svn: 183130
* R600/SI: Use a multiclass for MUBUF_Load_HelperTom Stellard2013-05-201-11/+23
| | | | | | | This will simplify the instructions and also the pattern definitions. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182288
* R600/SI: Add patterns for 64-bit shift operationsTom Stellard2013-05-201-0/+13
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182284
* R600/SI: Use the same names for VOP3 operands and encoding fieldsTom Stellard2013-05-201-6/+6
| | | | | | | | This makes it possible to reorder the operands without breaking the encoding. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182283
* R600/SI: Add intrinsic for texture image loadingTom Stellard2013-05-061-2/+17
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181267
* R600/SI: Use InstFlag for VOP3 modifier operandsTom Stellard2013-04-191-2/+2
| | | | | | | InstFlag has a default value of 0 and will simplify the VOP3 patterns. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 179829
* R600/SI: dynamical figure out the reg class of MIMGChristian Konig2013-04-101-0/+2
| | | | | | | | Depending on the number of bits set in the writemask. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 179166
* R600/SI: adjust writemask to only the used componentsChristian Konig2013-04-101-0/+8
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 179165
* R600/SI: Add support for buffer stores v2Tom Stellard2013-04-051-0/+26
| | | | | | | | v2: - Use the ADDR64 bit Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 178931
* R600/SI: Use same names for corresponding MUBUF operands and encoding fieldsTom Stellard2013-04-051-2/+2
| | | | | | | | | | | The code emitter knows how to encode operands whose name matches one of the encoding fields. If there is no match, the code emitter relies on the order of the operand and field definitions to determine how operands should be encoding. Matching by order makes it easy to accidentally break the instruction encodings, so we prefer to match by name. Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 178930
* R600/SI: add cummuting of rev instructionsChristian Konig2013-03-271-10/+36
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178127
* R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLEChristian Konig2013-03-261-1/+1
| | | | | | | Just define the address as unknown instead of VReg_32. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178022
* R600/SI: enable all S_LOAD and S_BUFFER_LOAD opcodesChristian Konig2013-03-181-3/+4
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 177272
* R600/SI: remove GPR*AlignEncodeChristian Konig2013-03-011-16/+6
| | | | | | | It's much easier to specify the encoding with tablegen directly. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 176344
* R600/SI: add VOP mapping functionsChristian Konig2013-02-261-11/+28
| | | | | | | | Make it possible to map between e32 and e64 encoding opcodes. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176104
* R600/SI: add post ISel folding for SI v2Christian Konig2013-02-261-9/+8
| | | | | | | | | | Include immediate folding and SGPR limit handling for VOP3 instructions. v2: remove leftover hasExtraSrcRegAllocReq Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176101
* R600/SI: fix VOP3b encoding v2Christian Konig2013-02-261-0/+24
| | | | | | | | | | v2: document why we hardcode VCC for now. This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176099
* R600/SI: add the missing M*BUF|IMG asm operandsChristian Konig2013-02-211-4/+8
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175753
* R600/SI: add the missing S_* asm operandsChristian Konig2013-02-211-18/+34
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175752
* R600/SI: rework VOP3 classesChristian Konig2013-02-211-14/+14
| | | | | | | | | Order the classes and add asm operands. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175751
* R600/SI: simplify VOPC_* pattern v2Christian Konig2013-02-211-7/+16
| | | | | | | | | | | Fixing asm operation names. v2: fix name of the e64 encoding, also add asm operands Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175750
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