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* R600/SI: Update VOP3b to not include obsolete operandsMatt Arsenault2014-09-301-3/+5
| | | | | | abs / neg are now part of the srcN_modifiers operands llvm-svn: 218691
* R600/SI: Add support for global atomic addTom Stellard2014-09-251-2/+79
| | | | llvm-svn: 218457
* R600/SI: Clean up checks for legality of immediate operandsTom Stellard2014-09-231-2/+2
| | | | | | | | | | | | | | There are new register classes VCSrc_* which represent operands that can take an SGPR, VGPR or inline constant. The VSrc_* class is now used to represent operands that can take an SGPR, VGPR, or a 32-bit immediate. This allows us to have more accurate checks for legality of immediates, since before we had no way to distinguish between operands that supported any 32-bit immediate and operands which could only support inline constants. llvm-svn: 218334
* Revert "R600/SI: Add support for global atomic add"Tom Stellard2014-09-221-79/+2
| | | | | | | | | This reverts commit r218254. The global_atomics.ll test fails with asserts disabled. For some reason, the compiler fails to produce the atomic no return variants. llvm-svn: 218257
* R600/SI: Add support for global atomic addTom Stellard2014-09-221-2/+79
| | | | llvm-svn: 218254
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-151-0/+25
| | | | llvm-svn: 217777
* R600/SI: Replace LDS atomics with no return versionsMatt Arsenault2014-09-081-0/+4
| | | | llvm-svn: 217379
* R600/SI: Add InstrMapping for noret atomics.Matt Arsenault2014-09-081-9/+35
| | | | | | | | Only handles LDS atomics for now, and will be used to replace atomics with no uses with the no return versions. llvm-svn: 217378
* R600/SI: Use mad for fsub + fmulMatt Arsenault2014-08-291-0/+11
| | | | | | | We can use a negate source modifier to match this for fsub. llvm-svn: 216735
* R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops with 32-bit alignmentTom Stellard2014-08-221-0/+1
| | | | llvm-svn: 216279
* R600/SI: Use a ComplexPattern for DS loads and storesTom Stellard2014-08-221-0/+2
| | | | llvm-svn: 216278
* R600/SI: Use correct helper class for DS_WRITE2 instructionsTom Stellard2014-08-221-1/+1
| | | | | | | DS_1A uses a single offset encoding, so offset1 wasn't being encoded. llvm-svn: 216276
* R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variantTom Stellard2014-08-111-3/+34
| | | | | | | This saves us from having to copy a 64-bit 0 value into VGPRs for BUFFER_* instruction which only have a 12-bit immediate offset. llvm-svn: 215399
* R600/SI: Add an _OFFEN variant MUBUF_STORE_* and use it for scratch writesTom Stellard2014-08-111-11/+24
| | | | llvm-svn: 215398
* R600/SI: Clear lds bit on MUBUF instructions used for private storesTom Stellard2014-08-111-0/+1
| | | | | | | | This bit was left uninitialized, which was causing some random failures of piglit tests. NOTE: This is a candidate for the 3.5 branch. llvm-svn: 215396
* R600/SI: Update MUBUF assembly string to match AMD proprietary compilerTom Stellard2014-08-051-21/+46
| | | | llvm-svn: 214866
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-1/+1
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* R600/SI: Fix definitions for ds_read2 / ds_write2 instructions.Matt Arsenault2014-08-041-1/+2
| | | | | | | These were just wrong, using the wrong register classes and store2 was missing an operand. llvm-svn: 214756
* R600/SI: Fix extra whitespace in asm strMatt Arsenault2014-08-031-1/+1
| | | | | | | | | This slipped in in r214467, so something like V_MOV_B32_e32 v0, ... is now printed with 2 spaces between the instruction name and first operand. llvm-svn: 214660
* R600/SI: Don't display GDS bit for read2Matt Arsenault2014-08-011-1/+1
| | | | | | | This isn't displayed for any other instructions anymore, and isn't ever used. llvm-svn: 214523
* R600/SI: Do abs/neg folding with ComplexPatternsTom Stellard2014-08-011-152/+414
| | | | | | | | | | Abs/neg folding has moved out of foldOperands and into the instruction selection phase using complex patterns. As a consequence of this change, we now prefer to select the 64-bit encoding for most instructions and the modifier operands have been dropped from integer VOP3 instructions. llvm-svn: 214467
* R600/SI: Refactor VOP3 instruction definitionsTom Stellard2014-07-211-21/+50
| | | | llvm-svn: 213571
* R600/SI: Initailize encoding fields of unused VOP3 modifiers to 0Tom Stellard2014-07-211-0/+5
| | | | llvm-svn: 213564
* R600/SI: Initialize unused VOP3 sources to 0 instead of SIOperand.ZEROTom Stellard2014-07-211-6/+6
| | | | llvm-svn: 213563
* R600/SI: Add instruction shrinking passTom Stellard2014-07-211-0/+9
| | | | | | This pass converts 64-bit instructions to 32-bit when possible. llvm-svn: 213561
* R600/SI: VOPC instructions explicitly define VCCTom Stellard2014-07-211-1/+1
| | | | | | Therefore we don't need to add it to the implict defs list. llvm-svn: 213558
* R600/SI: Use scratch memory for large private arraysTom Stellard2014-07-211-20/+37
| | | | llvm-svn: 213551
* R600/SI: Remove vaddr operand from BUFFER_LOAD_*_OFFSET instructionsTom Stellard2014-07-211-2/+2
| | | | | | This operand is never used. llvm-svn: 213549
* R600/SI: Store constant initializer data in constant memoryTom Stellard2014-07-211-0/+4
| | | | | | | | | | | | This implements a solution for constant initializers suggested by Vadim Girlin, where we store the data after the shader code and then use the S_GETPC instruction to compute its address. This saves use the trouble of creating a new buffer for constant data and then having to pass the pointer to the kernel via user SGPRs or the input buffer. llvm-svn: 213530
* R600/SI: Use a custom encoding method for simm16 in SOPP branch instructionsTom Stellard2014-07-211-0/+9
| | | | | | | This allows us to explicitly define the type of fixup that is needed, so we can distinguish this from future fixup types. llvm-svn: 213527
* R600/SI: Use a ComplexPattern for ADDR64 addressing of MUBUF loadsTom Stellard2014-07-021-2/+6
| | | | llvm-svn: 212217
* R600/SI: Use a ComplexPattern for MUBUF storesTom Stellard2014-06-241-2/+9
| | | | | | | | Now that non-leaf ComplexPatterns are allowed we can fold all the MUBUF store patterns into the instruction definition. We will also be able to reuse this new ComplexPattern for MUBUF loads and atomic operations. llvm-svn: 211644
* R600/SI: Fix div_scale intrinsic.Matt Arsenault2014-06-231-0/+16
| | | | | | | The operand that must match one of the others does matter, and implement selecting for it. llvm-svn: 211523
* R600/SI: add gather4 and getlod intrinsics (v3)Marek Olsak2014-06-181-0/+47
| | | | | | | | | This contains all the previous patches + getlod support on top of it. It doesn't use SDNodes anymore, so it's quite small. It also adds v16i8 to SReg_128, which is used for the sampler descriptor. Reviewed-by: Tom Stellard llvm-svn: 211228
* R600/SI: Prettier operand printing for 64-bit ops.Matt Arsenault2014-06-181-3/+5
| | | | | | Copy what is done for 32-bit already so the order is about the same. llvm-svn: 211186
* R600/SI: Comparisons set vcc.Matt Arsenault2014-06-181-3/+13
| | | | llvm-svn: 211178
* R600/SI: Make sure target flags are set on pseudo VOP3 instructionsTom Stellard2014-06-171-1/+1
| | | | llvm-svn: 211120
* R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*Matt Arsenault2014-06-121-26/+0
| | | | | | | There is not such thing as a 0-data ds instruction, and the data operand needs to be a vgpr set to something meaningful. llvm-svn: 210756
* R600/SI: Add common 64-bit LDS atomicsMatt Arsenault2014-06-111-4/+4
| | | | llvm-svn: 210680
* R600/SI: Add instruction definitions for more LDS opsMatt Arsenault2014-06-111-0/+62
| | | | llvm-svn: 210675
* R600/SI: Implement i64 ctpopMatt Arsenault2014-06-101-0/+6
| | | | llvm-svn: 210568
* R600/SI: Rename VOP3 helper class to be more generalMatt Arsenault2014-06-091-1/+1
| | | | | | It has other uses besides shift instructions. llvm-svn: 210478
* R600/SI: Refactor the VOP3_32 tablegen classTom Stellard2014-05-161-3/+35
| | | | | | | | This will allow us to use a single MachineInstr to represent instructions which behave the same but have different encodings on some subtargets. llvm-svn: 209028
* R600/SI: Prettier display of input modifiersVincent Lejeune2014-05-101-21/+25
| | | | llvm-svn: 208479
* R600/SI: Fix SMRD pattern for offsets > 32 bitsTom Stellard2014-05-091-5/+4
| | | | | | We were dropping the high bits of 64-bit immediate offsets. llvm-svn: 208431
* R600/SI: Fix verifier error with pseudo store instructions.Matt Arsenault2014-05-011-1/+1
| | | | | | | | Use i32 instead of specifying SReg_32. When this is the pseudo INDIRECT_BASE_ADDR, this would give a bogus verifier error. llvm-svn: 207770
* R600/SI: Stop using i128 as the resource descriptor typeTom Stellard2014-04-171-4/+4
| | | | | | | | | Having i128 as a legal type complicates the legalization phase. v4i32 is already a legal type, so we will use that instead. This fixes several piglit tests. llvm-svn: 206500
* R600/SI: Print more immediates in hex formatMatt Arsenault2014-04-151-12/+12
| | | | | | | | | Print in decimal for inline immediates, and hex otherwise. Use hex always for offsets in addressing offsets. This approximately matches what the shader compiler does. llvm-svn: 206335
* R600/SI: Refactor SOPC classes slightly.Matt Arsenault2014-04-111-8/+10
| | | | | | | Better match what is done for VOPC to eventually prefer selecting these. llvm-svn: 206048
* R600/SI: Lower 64-bit immediates using REG_SEQUENCETom Stellard2014-04-031-2/+1
| | | | llvm-svn: 205561
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