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path: root/llvm/lib/Target/R600/SIInstrInfo.h
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* R600/SI: Teach moveToVALU how to handle some SMRD instructionsTom Stellard2014-04-301-0/+2
| | | | llvm-svn: 207660
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-28/+28
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition llvm-svn: 207503
* [C++] Use 'nullptr'.Craig Topper2014-04-281-1/+1
| | | | llvm-svn: 207394
* R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16Matt Arsenault2014-04-181-0/+1
| | | | llvm-svn: 206547
* R600/SI: Implement shouldConvertConstantLoadToIntImmMatt Arsenault2014-03-311-0/+1
| | | | llvm-svn: 205244
* R600/SI: Implement SIInstrInfo::isTriviallyRematerializable()Tom Stellard2014-03-311-0/+3
| | | | llvm-svn: 205188
* R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops.Matt Arsenault2014-03-241-1/+7
| | | | | | | No longer asserts, but now you get moves loading legal immediates into the split 32-bit operations. llvm-svn: 204661
* R600/SI: Fix 64-bit bit ops that require the VALU.Matt Arsenault2014-03-241-0/+5
| | | | | | | | Try to match scalar and first like the other instructions. Expand 64-bit ands to a pair of 32-bit ands since that is not available on the VALU. llvm-svn: 204660
* R600/SI: Move splitting 64-bit immediates to separate function.Matt Arsenault2014-03-241-0/+6
| | | | llvm-svn: 204651
* R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()Tom Stellard2014-03-211-0/+10
| | | | llvm-svn: 204476
* R600: Remove unused method declaration.Matt Arsenault2014-03-201-6/+0
| | | | llvm-svn: 204357
* Remove incomplete commentMatt Arsenault2014-03-111-2/+0
| | | | llvm-svn: 203518
* Move trivial getter into header.Matt Arsenault2014-03-111-1/+3
| | | | llvm-svn: 203517
* R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are usedTom Stellard2014-02-101-0/+1
| | | | | | | | | | | DS instructions that access local memory can only uses addresses that are less than or equal to the value of M0. When M0 is uninitialized, then we experience undefined behavior. This patch also changes the behavior to emit S_WQM_B64 on pixel shaders no matter what kind of DS instruction is used. llvm-svn: 201097
* Use llvm_unreachable instead of assert(0)Matt Arsenault2013-12-101-1/+4
| | | | llvm-svn: 196971
* R600/SI: Implement spilling of SGPRs v5Tom Stellard2013-11-271-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions. v2: - Fix encoding of Lane Mask - Use correct register flags, so we don't overwrite the low dword when restoring multi-dword registers. v3: - Register spilling seems to hang the GPU, so replace all shaders that need spilling with a dummy shader. v4: - Fix *LANE definitions - Change destination reg class for 32-bit SMRD instructions v5: - Remove small optimization that was crashing Serious Sam 3. https://bugs.freedesktop.org/show_bug.cgi?id=68224 https://bugs.freedesktop.org/show_bug.cgi?id=71285 NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195880
* Make method staticMatt Arsenault2013-11-151-1/+1
| | | | llvm-svn: 194858
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-4/+14
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-131-0/+36
| | | | | | | | | | | | | | All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. llvm-svn: 194625
* R600: Simplify handling of private address spaceTom Stellard2013-10-221-6/+4
| | | | | | | | | | | | | | | | | | The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. llvm-svn: 193179
* R600: Remove unused InstrInfo::getMovImmInstr() functionTom Stellard2013-10-221-3/+0
| | | | llvm-svn: 193178
* Fix missing C++ mode thing in headerMatt Arsenault2013-10-151-1/+1
| | | | llvm-svn: 192751
* R600/SI: Implement SIInstrInfo::verifyInstruction() for VOP*Tom Stellard2013-10-101-1/+9
| | | | | | | The function is used by the machine verifier and checks that VOP* instructions have legal operands. llvm-svn: 192367
* R600/SI: Fix broken encoding of DS_WRITE_B32Michel Danzer2013-08-161-0/+1
| | | | | | | | | | | | | | The logic in SIInsertWaits::getHwCounts() only really made sense for SMRD instructions, and trying to shoehorn it into handling DS_WRITE_B32 caused it to corrupt the encoding of that by clobbering the first operand with the second one. Undo that damage and only apply the SMRD logic to that. Fixes some derivates related piglit regressions with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 188558
* R600/SI: Assign a register class to the $vaddr operand for MIMG instructionsTom Stellard2013-08-141-1/+1
| | | | | | | The previous code declared the operand as unknown:$vaddr, which made it possible for scalar registers to be used instead of vector registers. llvm-svn: 188425
* R600/SI: adjust writemask to only the used componentsChristian Konig2013-04-101-0/+1
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 179165
* R600/SI: add cummuting of rev instructionsChristian Konig2013-03-271-0/+4
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178127
* R600/SI: add VOP mapping functionsChristian Konig2013-02-261-0/+6
| | | | | | | | Make it possible to map between e32 and e64 encoding opcodes. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176104
* R600/SI: add some more instruction flagsChristian Konig2013-02-261-0/+3
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176102
* R600/SI: cleanup VGPR encodingTom Stellard2013-02-071-9/+3
| | | | | | | | | | Remove all the unused code. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174656
* R600: Support for indirect addressing v4Tom Stellard2013-02-061-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525
* R600: Proper insert S_WAITCNT instructionsTom Stellard2013-01-181-1/+3
| | | | | | | | | | | | | | | | Some instructions like memory reads/writes are executed asynchronously, so we need to insert S_WAITCNT instructions to block before accessing their results. Previously we have just inserted S_WAITCNT instructions after each async instruction, this patch fixes this and adds a prober insertion pass. Patch by: Christian König Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> llvm-svn: 172846
* Add R600 backendTom Stellard2012-12-111-0/+62
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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