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path: root/llvm/lib/Target/R600/SIInstrInfo.cpp
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* R600/SI: Commute instructions to enable more folding opportunitiesTom Stellard2015-01-071-1/+4
| | | | llvm-svn: 225410
* R600/SI: Remove VReg_32 register classTom Stellard2015-01-071-11/+11
| | | | | | | | | | | Use VGPR_32 register class instead. These two register classes were identical and having separate classes was causing SIInstrInfo::isLegalOperands() to be overly conservative in some cases. This change is necessary to prevent future paches from missing a folding opportunity in fneg-fabs.ll. llvm-svn: 225382
* R600/SI: Add a V_MOV_B64 pseudo instructionTom Stellard2015-01-071-0/+31
| | | | | | | This is used to simplify the SIFoldOperands pass and make it easier to fold immediates. llvm-svn: 225373
* R600/SI: Teach SIFoldOperands to split 64-bit constants when foldingTom Stellard2015-01-071-0/+10
| | | | | | | | | | | | | | | This allows folding of sequences like: s[0:1] = s_mov_b64 4 v_add_i32 v0, s0, v0 v_addc_u32 v1, s1, v1 into v_add_i32 v0, 4, v0 v_add_i32 v1, 0, v1 llvm-svn: 225369
* R600/SI: isLegalOperand() shouldn't check constant bus for SALU instructionsTom Stellard2014-12-191-1/+1
| | | | | | | The constant bus restrictions only apply to VALU instructions. This enables SIFoldOperands to fold immediates into SALU instructions. llvm-svn: 224623
* R600/SI: Fix f64 inline immediatesMatt Arsenault2014-12-171-12/+26
| | | | llvm-svn: 224458
* R600/SI: Handle physical registers in getOpRegClassMatt Arsenault2014-12-111-2/+7
| | | | llvm-svn: 224079
* R600/SI: Don't verify constant bus usage of flag opsMatt Arsenault2014-12-111-2/+10
| | | | | | | | | | | | This was checking if pseudo-operands like the source modifiers were using the constant bus, which happens to work because the values these all can be happen to be valid inline immediates. This fixes a later commit which starts checking the register class of the operands. llvm-svn: 224078
* R600/SI: Set 20-bit immediate byte offset for SMRD on VIMarek Olsak2014-12-071-13/+23
| | | | llvm-svn: 223614
* R600/SI: Update instruction conversions for VIMarek Olsak2014-12-071-0/+27
| | | | | | | | | There are 3 changes: - Convert 32-bit S_LSHL/LSHR/ASHR to their V_*REV variants for VI - Lower RSQ_CLAMP for VI - Don't generate MIN/MAX_LEGACY on VI llvm-svn: 223604
* R600/SI: Set the ATC bit on all resource descriptors for the HSA runtimeTom Stellard2014-12-021-4/+14
| | | | llvm-svn: 223125
* R600/SI: Various instruction format bit test cleanupsMatt Arsenault2014-12-011-52/+0
| | | | | | | | | | | - Fix missing SALU format bits - Remove unused isSALUInstr - Add isVALU - Switch isDS to use a bit like the others - Move SIInstrInfo::is* functions to header - Reorder so they are approximately sorted by type (SALU, VALU, memory) llvm-svn: 223038
* R600/SI: Add an s_mov_b32 to patterns which use the M0RegClassTom Stellard2014-11-211-20/+0
| | | | | | | We need to use a s_mov_b32 rather than a copy, so that CSE will eliminate redundant moves to the m0 register. llvm-svn: 222584
* R600/SI: Make SIInstrInfo::isOperandLegal() more strictTom Stellard2014-11-191-1/+10
| | | | | | | | | | | | A register operand that has a common sub-class with its instruction's defined register class is not always legal. For example, SReg_32 and M0Reg both have a common sub-class, but we can't use an SReg_32 in instructions that expect a M0Reg. This prevents the llvm.SI.sendmsg.ll test from failing when the fold operand pass is added. llvm-svn: 222368
* R600/SI: Implement areMemAccessesTriviallyDisjointMatt Arsenault2014-11-191-0/+83
| | | | | | | | | This partially makes up for not having address spaces used for alias analysis in some simple cases. This is not yet enabled by default so shouldn't change anything yet. llvm-svn: 222286
* R600/SI: Don't copy flags when extracting subregMatt Arsenault2014-11-171-6/+8
| | | | | | | | | This was resulting in use of a register after a kill. For some reason this showed up as a problem in many tests when moving the SIFixSGPRCopies pass closer to instruction selection. llvm-svn: 222175
* Fix unused variable warning without assertsMatt Arsenault2014-11-141-0/+2
| | | | llvm-svn: 222017
* R600/SI: Use S_BFE_I64 for 64-bit sext_inregMatt Arsenault2014-11-141-1/+65
| | | | llvm-svn: 222012
* R600/SI: Allow commuting with src2_modifiersMatt Arsenault2014-11-131-5/+0
| | | | llvm-svn: 221911
* Fix typoMatt Arsenault2014-10-171-1/+1
| | | | llvm-svn: 220068
* R600/SI: Allow commuting with source modifiersMatt Arsenault2014-10-171-11/+22
| | | | llvm-svn: 220066
* R600/SI: Fix general commuting breaking src modsMatt Arsenault2014-10-171-1/+13
| | | | | | | | The generic code trying to use findCommutedOpIndices won't understand that it needs to swap the modifier operands also, so it should fail if they are set. llvm-svn: 220064
* R600/SI: Allow comuting fp immediatesMatt Arsenault2014-10-171-3/+9
| | | | llvm-svn: 220062
* R600/SI: Use early return instead of checking condition twiceMatt Arsenault2014-10-171-11/+16
| | | | | | Any commutable instruction will have at least src1. llvm-svn: 220061
* R600/SI: Minor cleanup of functionMatt Arsenault2014-10-131-9/+11
| | | | llvm-svn: 219616
* R600/SI: Remove assertion in SIInstrInfo::areLoadsFromSameBasePtr()Tom Stellard2014-10-071-1/+4
| | | | | | | Added a FIXME coment instead, we need to handle the case where the two DS instructions being compared have different numbers of operands. llvm-svn: 219236
* R600/SI: Update VOP3b to not include obsolete operandsMatt Arsenault2014-09-301-4/+2
| | | | | | abs / neg are now part of the srcN_modifiers operands llvm-svn: 218691
* R600/SI: Use break instead of continueMatt Arsenault2014-09-261-1/+1
| | | | | | If an instruction doesn't have src1, it doesn't have src2 llvm-svn: 218536
* R600/SI: Move finding SGPR operand to move to separate functionMatt Arsenault2014-09-261-63/+69
| | | | llvm-svn: 218533
* R600/SI Allow same SGPR to be used for multiple operandsMatt Arsenault2014-09-261-5/+32
| | | | | | | | | | | Instead of moving the first SGPR that is different than the first, legalize the operand that requires the fewest moves if one SGPR is used for multiple operands. This saves extra moves and is also required for some instructions which require that the same operand be used for multiple operands. llvm-svn: 218532
* R600/SI: Partially move operand legalization to post-isel hook.Matt Arsenault2014-09-261-10/+29
| | | | | | | | | Disable the SGPR usage restriction parts of the DAG legalizeOperands. It now should only be doing immediate folding until it can be replaced later. The real legalization work is now done by the other SIInstrInfo::legalizeOperands llvm-svn: 218531
* R600/SI: Implement findCommutedOpIndicesMatt Arsenault2014-09-261-0/+32
| | | | | | | | | | | The base implementation of commuteInstruction is used in some cases, but it turns out this has been broken for a long time since modifiers were inserted between the real operands. The base implementation of commuteInstruction also fails on immediates, which also needs to be fixed. llvm-svn: 218530
* R600/SI: Don't move operands that are required to be SGPRsMatt Arsenault2014-09-261-1/+20
| | | | | | | | e.g. v_cndmask_b32 requires the condition operand be an SGPR. If one of the source operands were an SGPR, that would be considered the one SGPR use and the condition operand would be illegally moved. llvm-svn: 218529
* R600/SI: Don't assert on exotic operand typesMatt Arsenault2014-09-261-1/+1
| | | | | | | | | This needs a test, but I'm not sure if it is currently possible and I originally hit it due to a bug. Right now the only global address operands have no reason to be VALU instructions, although it theoretically could be a problem. llvm-svn: 218528
* R600/SI: Fix using wrong operand indices when commutingMatt Arsenault2014-09-261-11/+20
| | | | | | | | | | | | | No test since the current SIISelLowering::legalizeOperands effectively hides this, and the general uses seem to only fire on SALU instructions which don't have modifiers between the operands. When trying to use legalizeOperands immediately after instruction selection, it now sees a lot more patterns it did not see before which break on this. llvm-svn: 218527
* Silencing an "enumeral and non-enumeral type in conditional expression" ↵Aaron Ballman2014-09-241-1/+2
| | | | | | warning. NFC. llvm-svn: 218381
* R600/SI: Fix hardcoded and wrong operand numbers.Matt Arsenault2014-09-241-5/+3
| | | | | | Also fix leftover debug printing llvm-svn: 218359
* R600/SI: Fix the FixSGPRLiveRanges passTom Stellard2014-09-241-0/+4
| | | | | | | | | | | The previous implementation was extending the live range of SGPRs by modifying the live intervals directly. This was causing a lot of machine verification errors when the machine scheduler was enabled. The new implementation adds pseudo instructions with implicit uses to extend the live ranges of SGPRs, which works much better. llvm-svn: 218351
* R600/SI: Implement VGPR register spilling for compute at -O0 v3Tom Stellard2014-09-241-28/+158
| | | | | | | | | | | | | | VGPRs are spilled to LDS. This still needs more testing, but we need to at least enable it at -O0, because the fast register allocator spills all registers that are live at the end of blocks and without this some future commits will break the flat-address-space.ll test. v2: Only calculate thread id once v3: Move insertion of spill instructions to SIRegisterInfo::eliminateFrameIndex() llvm-svn: 218348
* R600/SI: Clean up checks for legality of immediate operandsTom Stellard2014-09-231-35/+59
| | | | | | | | | | | | | | There are new register classes VCSrc_* which represent operands that can take an SGPR, VGPR or inline constant. The VSrc_* class is now used to represent operands that can take an SGPR, VGPR, or a 32-bit immediate. This allows us to have more accurate checks for legality of immediates, since before we had no way to distinguish between operands that supported any 32-bit immediate and operands which could only support inline constants. llvm-svn: 218334
* Fix typoMatt Arsenault2014-09-231-2/+3
| | | | llvm-svn: 218324
* R600/SI: Remove assertMatt Arsenault2014-09-171-6/+7
| | | | | | | | | | Since read2 / write2 are emitted for 4-byte aligned 8-byte accesses, these are seen by the scheduler. The DAG scheduler is semi-deprecated, so just ignore these for now. llvm-svn: 217969
* R600/SI: Rough first implementation of shouldClusterLoadsMatt Arsenault2014-09-171-0/+22
| | | | llvm-svn: 217968
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-151-0/+8
| | | | llvm-svn: 217777
* R600/SI: Report offset in correct units for st64 DS instructionsMatt Arsenault2014-09-101-0/+15
| | | | | | | | | | | Need to convert the 64 element offset into bytes, not just the element size like the normal case instructions. Noticed by inspection. This can't be hit now because st64 instructions aren't emitted during instruction selection, and the post-RA scheduler isn't enabled. llvm-svn: 217560
* R600/SI: Fix bug in SIInstrInfo::legalizeOpWithMove()Tom Stellard2014-09-051-4/+5
| | | | | | | | | | We must constrain the destination register class of legalized operands to a VGPR class or else the illegal operand may be folded back into the instruction by the register coalescer. This fixes a bug in add.ll that will be uncovered by future commits. llvm-svn: 217249
* R600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of 64-bit operationsTom Stellard2014-09-051-3/+5
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=83416 llvm-svn: 217248
* R600/SI: Try to keep i32 mul on SALUMatt Arsenault2014-09-031-0/+5
| | | | | | | Also fix bug this exposed where when legalizing an immediate operand, a v_mov_b32 would be created with a VSrc dest register. llvm-svn: 217108
* R600/SI: Fix typos in SIInstrInfo::areLoadsFromSameBasePtr()Tom Stellard2014-09-031-2/+2
| | | | | | | | | | This fixes a crash in the OpenCV test: ImgprocWarpResizeArea/Resize.Mat/16 There is no test case for this, because this failure depends on a specific ordering of the loads, which could easily change. llvm-svn: 217040
* R600/SI: Teach moveToVALU how to handle more S_LOAD_* instructionsTom Stellard2014-08-211-9/+121
| | | | llvm-svn: 216220
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