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path: root/llvm/lib/Target/R600/R600InstrInfo.cpp
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* R600: Add local memory support via LDSTom Stellard2013-06-281-8/+38
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185162
* R600: Add support for GROUP_BARRIER instructionTom Stellard2013-06-281-0/+10
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185161
* R600: Add ALUInst bit to tablegen definitions v2Tom Stellard2013-06-281-3/+1
| | | | | | | | v2: - Remove functions left over from a previous rebase. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185160
* R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard2013-06-251-116/+74
| | | | llvm-svn: 184880
* R600: PV stores Reg id, not indexVincent Lejeune2013-06-171-1/+1
| | | | llvm-svn: 184117
* R600: Rework subtarget info and remove AMDILDevice classesTom Stellard2013-06-071-1/+1
| | | | | | | | This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-1/+1
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183561
* R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard2013-06-051-2/+4
| | | | | Reviewed-by: vljn at ovi.com llvm-svn: 183294
* R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune2013-06-041-0/+35
| | | | llvm-svn: 183278
* Move passes from namespace llvm into anonymous namespaces. Sort includes ↵Benjamin Kramer2013-05-231-1/+1
| | | | | | while there. llvm-svn: 182594
* R600: Relax some vector constraints on Dot4.Vincent Lejeune2013-05-171-3/+89
| | | | | | | | | | Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register coalescer to remove some unneeded COPY. This patch also defines some structures/functions that can be used to handle every vector instructions (CUBE, Cayman special instructions...) in a similar fashion. llvm-svn: 182126
* R600: Some factorizationVincent Lejeune2013-05-171-24/+162
| | | | llvm-svn: 182123
* R600: Remove dead code from the CodeEmitter v2Tom Stellard2013-05-061-3/+2
| | | | | | | | | v2: - Replace switch statement with TSFlags query Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181229
* R600: Always use texture cache for compute shadersVincent Lejeune2013-04-301-2/+6
| | | | | | This will improve the performance of memory reads. llvm-svn: 180762
* R600: Packetize instructionsVincent Lejeune2013-04-301-1/+10
| | | | llvm-svn: 180760
* R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chipsVincent Lejeune2013-04-301-0/+8
| | | | llvm-svn: 180759
* R600: Add a Bank Swizzle operandVincent Lejeune2013-04-301-1/+2
| | | | llvm-svn: 180758
* R600: Add FetchInst bit to instruction defs to denote vertex/tex instructionsVincent Lejeune2013-04-301-1/+19
| | | | | | v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache llvm-svn: 180755
* R600: Factorize maximum alu per clause in a single locationVincent Lejeune2013-04-031-0/+3
| | | | llvm-svn: 178667
* R600: Factorize code handling Const Read Port limitationVincent Lejeune2013-03-141-0/+54
| | | | llvm-svn: 177078
* R600: Fix JUMP handling so that MachineInstr verification can occurVincent Lejeune2013-03-111-31/+35
| | | | | | This allows R600 Target to use the newly created -verify-misched llc flag llvm-svn: 176819
* R600: Do not predicate vector opVincent Lejeune2013-03-051-0/+2
| | | | llvm-svn: 176507
* R600: Support for indirect addressing v4Tom Stellard2013-02-061-0/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525
* R600: improve inputs/interpolation handlingTom Stellard2013-02-051-1/+0
| | | | | | | | | | | | | | | | Use one intrinsic for all sorts of interpolation. Use two separate unexpanded instructions to represent INTERP_XY and _ZW - this will allow to eliminate one part if it's not used. Track liveness of special interpolation regs instead of reserving them - this will allow to reuse those regs, lowering reg pressure. Patch By: Vadim Girlin v2[Vincent Lejeune]: Rebased against current llvm master Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174394
* R600: rework handling of the constantsTom Stellard2013-01-231-13/+5
| | | | | | | | | | | | | | | | | | | | Remove Cxxx registers, add new special register - "ALU_CONST" and new operand for each alu src - "sel". ALU_CONST is used to designate that the new operand contains the value to override src.sel, src.kc_bank, src.chan for constants in the driver. Patch by: Vadim Girlin Vincent Lejeune: - Use pointers for constants - Fold CONST_ADDRESS when possible Tom Stellard: - Give CONSTANT_BUFFER_0 its own address space - Use integer types for constant loads Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 173222
* Resort the #include lines in include/... and lib/... with theChandler Carruth2013-01-021-1/+1
| | | | | | | | | | utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. llvm-svn: 171362
* Target/R600: Update MIB according to r170588.NAKAMURA Takumi2012-12-201-5/+7
| | | | llvm-svn: 170620
* Fix warnings with -DNDEBUGTom Stellard2012-12-131-0/+1
| | | | | | Patch by: NAKAMURA Takumi llvm-svn: 170142
* Add R600 backendTom Stellard2012-12-111-0/+663
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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