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path: root/llvm/lib/Target/R600/AMDGPUMCInstLower.cpp
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* Grab the subtarget off of the machine function for the R600Eric Christopher2015-02-191-5/+4
| | | | | | asm printer and clean up a bunch of uses. llvm-svn: 229803
* Remove the DisasmEnabled AsmPrinter variable and just look itEric Christopher2015-02-191-1/+1
| | | | | | | up on the subtarget where it's set anyhow than looking it up 2-3 times in the same place. llvm-svn: 229802
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-301-5/+6
| | | | | | without a Function argument. llvm-svn: 227638
* R600/SI: Use external symbols for scratch bufferTom Stellard2015-01-201-0/+6
| | | | | | | | We were passing the scratch buffer address to the shaders via user sgprs, but now we use external symbols and have the driver patch the shader using reloc information. llvm-svn: 226586
* R600/SI: Don't shrink instructions whose e32 encoding doesn't existMarek Olsak2015-01-151-20/+9
| | | | | | | | v2: modify hasVALU32BitEncoding instead v3: - add pseudoToMCOpcode helper to AMDGPUInstInfo, which is used by both hasVALU32BitEncoding and AMDGPUMCInstLower::lower - report an error if a pseudo can't be lowered llvm-svn: 226188
* R600/SI: Add pattern for bitcasting fp immediates to integersTom Stellard2015-01-131-12/+0
| | | | | | | | The backend now assumes that all immediates are integers. This allows us to simplify immediate handling code, becasue we no longer need to handle fp and integer immediates differently. llvm-svn: 225844
* R600/SI: Fix f64 inline immediatesMatt Arsenault2014-12-171-3/+8
| | | | llvm-svn: 224458
* R600/SI: Add VI instructionsMarek Olsak2014-12-071-2/+7
| | | | llvm-svn: 223603
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-3/+4
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* R600/SI: Store constant initializer data in constant memoryTom Stellard2014-07-211-0/+16
| | | | | | | | | | | | This implements a solution for constant initializers suggested by Vadim Girlin, where we store the data after the shader code and then use the S_GETPC instruction to compute its address. This saves use the trouble of creating a new buffer for constant data and then having to pass the pointer to the kernel via user SGPRs or the input buffer. llvm-svn: 213530
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-0/+1
| | | | llvm-svn: 210869
* Resolving MSVC warnings about switch statements with a default label, but no ↵Aaron Ballman2014-05-191-4/+2
| | | | | | case labels. No functional changes intended. llvm-svn: 209126
* R600/SI: Refactor the VOP3_32 tablegen classTom Stellard2014-05-161-4/+24
| | | | | | | | This will allow us to use a single MachineInstr to represent instructions which behave the same but have different encodings on some subtargets. llvm-svn: 209028
* MachineInstr: introduce explicit_operands and implicit_operands rangesDavid Blaikie2014-04-051-3/+1
| | | | | | | Makes iteration over implicit and explicit machine operands more explicit (har har). Insipired by code review discussion for r205565. llvm-svn: 205680
* R600: Verify all instructions in the AsmPrinter on debug buildsTom Stellard2014-02-281-0/+7
| | | | | | | Make a call to R600's implementation of verifyInstruction() to check that instructions are only using legal operands. llvm-svn: 202544
* Explictly pass MCSubtargetInfo to MCCodeEmitter::EncodeInstruction()David Woodhouse2014-01-281-1/+2
| | | | llvm-svn: 200348
* Change MCStreamer EmitInstruction interface to take subtarget infoDavid Woodhouse2014-01-281-1/+1
| | | | llvm-svn: 200345
* R600: Store disassembly in a special ELF section when feature +DumpCode is ↵Tom Stellard2013-10-121-4/+39
| | | | | | | | | enabled. Patch by: Jay Cornwall Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 192523
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-1/+1
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Resort the #include lines in include/... and lib/... with theChandler Carruth2013-01-021-1/+1
| | | | | | | | | | utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. llvm-svn: 171362
* R600: BB operand support for SITom Stellard2012-12-171-2/+8
| | | | | | | | | Patch by: Christian König Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> llvm-svn: 170342
* Add R600 backendTom Stellard2012-12-111-0/+77
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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