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author | Tom Stellard <thomas.stellard@amd.com> | 2013-10-12 05:02:51 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2013-10-12 05:02:51 +0000 |
commit | ed699259989868985a1a220d745161576242f4c9 (patch) | |
tree | 3d4a42cae55b81171804d3c1241922b4b9d2db29 /llvm/lib/Target/R600/AMDGPUMCInstLower.cpp | |
parent | aab53e7785fa4857b9ecc959f028b70356ab1052 (diff) | |
download | bcm5719-llvm-ed699259989868985a1a220d745161576242f4c9.tar.gz bcm5719-llvm-ed699259989868985a1a220d745161576242f4c9.zip |
R600: Store disassembly in a special ELF section when feature +DumpCode is enabled.
Patch by: Jay Cornwall
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 192523
Diffstat (limited to 'llvm/lib/Target/R600/AMDGPUMCInstLower.cpp')
-rw-r--r-- | llvm/lib/Target/R600/AMDGPUMCInstLower.cpp | 43 |
1 files changed, 39 insertions, 4 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUMCInstLower.cpp b/llvm/lib/Target/R600/AMDGPUMCInstLower.cpp index 1dc1c657dfe..0ed598ee8c0 100644 --- a/llvm/lib/Target/R600/AMDGPUMCInstLower.cpp +++ b/llvm/lib/Target/R600/AMDGPUMCInstLower.cpp @@ -15,14 +15,19 @@ #include "AMDGPUMCInstLower.h" #include "AMDGPUAsmPrinter.h" +#include "InstPrinter/AMDGPUInstPrinter.h" #include "R600InstrInfo.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/IR/Constants.h" +#include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCObjectStreamer.h" #include "llvm/MC/MCStreamer.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/Format.h" +#include <algorithm> using namespace llvm; @@ -69,15 +74,45 @@ void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { MachineBasicBlock::const_instr_iterator I = MI; ++I; while (I != MBB->end() && I->isInsideBundle()) { - MCInst MCBundleInst; - const MachineInstr *BundledInst = I; - MCInstLowering.lower(BundledInst, MCBundleInst); - OutStreamer.EmitInstruction(MCBundleInst); + EmitInstruction(I); ++I; } } else { MCInst TmpInst; MCInstLowering.lower(MI, TmpInst); OutStreamer.EmitInstruction(TmpInst); + + if (DisasmEnabled) { + // Disassemble instruction/operands to text. + DisasmLines.resize(DisasmLines.size() + 1); + std::string &DisasmLine = DisasmLines.back(); + raw_string_ostream DisasmStream(DisasmLine); + + AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *TM.getInstrInfo(), + *TM.getRegisterInfo()); + InstPrinter.printInst(&TmpInst, DisasmStream, StringRef()); + + // Disassemble instruction/operands to hex representation. + SmallVector<MCFixup, 4> Fixups; + SmallVector<char, 16> CodeBytes; + raw_svector_ostream CodeStream(CodeBytes); + + MCObjectStreamer &ObjStreamer = (MCObjectStreamer &)OutStreamer; + MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter(); + InstEmitter.EncodeInstruction(TmpInst, CodeStream, Fixups); + CodeStream.flush(); + + HexLines.resize(HexLines.size() + 1); + std::string &HexLine = HexLines.back(); + raw_string_ostream HexStream(HexLine); + + for (size_t i = 0; i < CodeBytes.size(); i += 4) { + unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i]; + HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord); + } + + DisasmStream.flush(); + DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size()); + } } } |