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* R600: Implement ComputeNumSignBitsForTargetNode for BFEMatt Arsenault2014-05-221-0/+25
| | | | llvm-svn: 209460
* R600: Implement computeMaskedBitsForTargetNode for BFEMatt Arsenault2014-05-221-1/+29
| | | | llvm-svn: 209459
* R600: Add intrinsics for mad24Matt Arsenault2014-05-221-0/+10
| | | | llvm-svn: 209456
* R600: Add comment describing problems with LowerConstantInitializerMatt Arsenault2014-05-211-0/+10
| | | | llvm-svn: 209333
* R600: Partially fix constant initializers for structs and vectors.Matt Arsenault2014-05-211-6/+33
| | | | | | | This should extend the current workaround to work with structs that only contain legal, scalar types. llvm-svn: 209331
* Use cast<> instead of unchecked dyn_castMatt Arsenault2014-05-211-1/+1
| | | | llvm-svn: 209310
* Use range forMatt Arsenault2014-05-151-6/+2
| | | | llvm-svn: 208922
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-141-14/+14
| | | | | | inappropriate since it lost its Mask parameter in r154011. llvm-svn: 208811
* R600: Add mul24 intrinsicsMatt Arsenault2014-05-121-0/+8
| | | | llvm-svn: 208604
* Fix return before elseMatt Arsenault2014-05-111-18/+18
| | | | llvm-svn: 208510
* R600: Expand i64 SELECT_CCTom Stellard2014-05-091-0/+2
| | | | llvm-svn: 208430
* R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()Tom Stellard2014-05-091-9/+13
| | | | llvm-svn: 208429
* R600: Promote f64 vector load/stores to i64 for consistencyMatt Arsenault2014-05-081-0/+6
| | | | llvm-svn: 208344
* R600: Expand i64 ISD:SUBTom Stellard2014-05-051-0/+1
| | | | llvm-svn: 208005
* R600: Expand vector sin and cos.Tom Stellard2014-05-021-0/+2
| | | | | | | | v2: move code to AMDGPUISelLowering.cpp squash with tests (both EG and SI) Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 207845
* R600: Expand TruncStore i64 -> {i16,i8}Tom Stellard2014-05-021-0/+2
| | | | llvm-svn: 207844
* R600: optimize the UDIVREM 64 algorithmTom Stellard2014-04-291-22/+44
| | | | | | | | | | | | | | | | This is a squash of several optimization commits: - calculate DIV_Lo and DIV_Hi separately - use BFE_U32 if we are operating on 32bit values - use precomputed constants instead of shifting in UDVIREM - skip the first 32 iterations of udivrem v2: Check whether BFE is supported before using it Patch by: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207589
* R600: Implement iterative algorithm for udivremTom Stellard2014-04-291-0/+50
| | | | | | | | | | Initial implementation, rather slow Patch by: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207588
* R600: Change UDIV/UREM to UDIVREM when legalizing typesTom Stellard2014-04-291-1/+19
| | | | | | | | | | | | | | | | | | When legalizing ops, with UDIV/UREM set to expand, they automatically expand to UDIVREM (if legal or custom). We need to do this manually for legalize types. v2: SI should be set to Expand because the type is legal, and it is automatically lowered to UDIVREM if UDIVREM is Legal/Custom R600 should set to UDIV/UREM to Custom because it needs to lower them during type legalization Patch by: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207587
* R600: remove unused variableTom Stellard2014-04-291-2/+0
| | | | | | | | Patch by: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207586
* Convert more SelectionDAG functions to use ArrayRef.Craig Topper2014-04-281-1/+1
| | | | llvm-svn: 207397
* Convert SelectionDAG::getMergeValues to use ArrayRef.Craig Topper2014-04-271-1/+1
| | | | llvm-svn: 207374
* Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>.Craig Topper2014-04-261-10/+6
| | | | llvm-svn: 207327
* R600: Fix function name printing in LowerCallMatt Arsenault2014-04-251-1/+3
| | | | | | | | v2: Check both ExternalSymbol and GlobalAddress Patch by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 207282
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-1/+1
| | | | llvm-svn: 207197
* R600: Emit error instead of unreachable on function callMatt Arsenault2014-04-221-0/+59
| | | | llvm-svn: 206904
* R600: Change how vector truncating stores are packed.Matt Arsenault2014-04-221-11/+25
| | | | | | | Don't introduce new operations on an illegal sub 32-bit type. Do the operations on a 32-bit value, and then use a truncating store. llvm-svn: 206864
* R600: Make sign_extend_inreg legal.Matt Arsenault2014-04-221-70/+11
| | | | | | Don't know why I didn't just do this in the first place. llvm-svn: 206862
* R600: Add comment clariying use of sext for result of MUL_U24Tom Stellard2014-04-171-0/+2
| | | | llvm-svn: 206501
* R600: Expand sign extension of vectors.Matt Arsenault2014-04-161-16/+0
| | | | | | | | | | | | | | Setting vector types to expand will result in scalarization on pre SI hw, as those gpus don't have vector shifts either. Expand also i32 vectors, this helps llvm make the correct decision about scalarizing the vector ops. v2: move setOperation() calls to R600ISelLowering.cpp. cleanup the SI code to make it obvious that this patch does is nop for SI Patch by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 206348
* R600/SI: Fix loads of i1Matt Arsenault2014-04-151-0/+14
| | | | llvm-svn: 206330
* Break PseudoSourceValue out of the Value hierarchy. It is now the root of ↵Nick Lewycky2014-04-151-1/+2
| | | | | | its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't). Anything that needs to use either a PseudoSourceValue* and Value* is strongly encouraged to use a MachinePointerInfo instead. llvm-svn: 206255
* Move ExtractVectorElements to SelectionDAG.Matt Arsenault2014-04-111-20/+6
| | | | | | | This seems generally useful, and makes sense to go along with SplitVector. llvm-svn: 206041
* R600: Match 24-bit arithmetic patterns in a Target DAGCombineTom Stellard2014-04-071-0/+84
| | | | | | | | | | | | | | | | | Moving these patterns from TableGen files to PerformDAGCombine() should allow us to generate better code by eliminating unnecessary shifts and extensions earlier. This also fixes a bug where the MAD pattern was calling SimplifyDemandedBits with a 24-bit mask on the first operand even when the full pattern wasn't being matched. This occasionally resulted in some instructions being incorrectly deleted from the program. v2: - Fix bug with 64-bit mul llvm-svn: 205731
* Use .data() instead of &x[0]Matt Arsenault2014-04-071-9/+10
| | | | llvm-svn: 205722
* R600: Compute masked bits for min and maxMatt Arsenault2014-03-311-0/+44
| | | | llvm-svn: 205242
* R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.Matt Arsenault2014-03-311-0/+24
| | | | llvm-svn: 205236
* R600: Add target nodes for BFM and BFIMatt Arsenault2014-03-311-0/+2
| | | | llvm-svn: 205235
* R600: Implement isZExtFree.Matt Arsenault2014-03-271-0/+16
| | | | | | | This allows 64-bit operations that are truncated to be reduced to 32-bit ones. llvm-svn: 204946
* R600/SI: Fix unreachable with a sext_in_reg to an illegal type.Matt Arsenault2014-03-271-0/+18
| | | | llvm-svn: 204945
* R600: Add a testcase for sext_in_reg I missed.Matt Arsenault2014-03-261-0/+2
| | | | | | This sext_inreg i32 in i64 case was already handled, but not enabled. llvm-svn: 204840
* R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cppMatt Arsenault2014-03-251-0/+9
| | | | | | | | Remove handling of select_cc, since it makes no sense to be there. This now does nothing, but I'll be adding some handling of other target nodes soon. llvm-svn: 204743
* R600: Implement isNarrowingProfitable.Matt Arsenault2014-03-241-0/+10
| | | | llvm-svn: 204658
* R600: Match sign_extend_inreg to BFE instructionsMatt Arsenault2014-03-171-0/+111
| | | | llvm-svn: 204072
* R600: Remove unnecessary attempt to zext a pointer.Matt Arsenault2014-03-151-3/+6
| | | | | | Private pointers are now always 32-bits. llvm-svn: 203989
* R600: Code cleanup.Matt Arsenault2014-03-151-11/+12
| | | | | | | Use sign_extend_inreg and getZeroExtendInReg instead of using the bit operations they expand into. llvm-svn: 203988
* R600: Fix trunc store from i64 to i1Matt Arsenault2014-03-121-0/+6
| | | | llvm-svn: 203695
* R600: Calculate store mask instead of using switch.Matt Arsenault2014-03-111-17/+3
| | | | llvm-svn: 203527
* Use .data() instead of &x[0]Matt Arsenault2014-03-111-2/+2
| | | | llvm-svn: 203516
* R600: Fix extloads from i8 / i16 to i64.Matt Arsenault2014-03-061-2/+14
| | | | | | | This appears to only be working for global loads. Private and local break for other reasons. llvm-svn: 203135
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