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* R600: Fix vector FMAMatt Arsenault2014-06-261-0/+1
| | | | llvm-svn: 211757
* R600: Promote i64 stores to v2i32Tom Stellard2014-06-241-0/+3
| | | | | | Now we need only one 64-bit pattern for stores. llvm-svn: 211643
* R600: Fix inconsistency in rsq instructions.Matt Arsenault2014-06-241-0/+8
| | | | | | | | | | | | | R600 was using a clamped version of rsq, but SI was not. Add a new rsq_clamped intrinsic and use them consistently. It's unclear to me from the documentation what behavior the R600 instructions have, so I assume they have the legacy behavior described by the SI documents. For R600, use RECIPSQRT_IEEE for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also has RECIPSQRT_FF, which I'm not sure how it fits in here. llvm-svn: 211637
* R600: Remove DIV_INFMatt Arsenault2014-06-241-2/+2
| | | | | | | This corresponded to an amdil instruction which there is a 2 instruction equivalent for. llvm-svn: 211616
* R600/SI: Fix div_scale intrinsic.Matt Arsenault2014-06-231-2/+14
| | | | | | | The operand that must match one of the others does matter, and implement selecting for it. llvm-svn: 211523
* R600: Remove AMDILISelLoweringMatt Arsenault2014-06-231-7/+0
| | | | llvm-svn: 211519
* R600: Select is not expensive.Matt Arsenault2014-06-231-0/+7
| | | | llvm-svn: 211518
* R600: Move add/sub with overflow out of AMDILISelLoweringMatt Arsenault2014-06-231-0/+4
| | | | | | Add more tests for these. llvm-svn: 211517
* R600: Move more out of AMDILISelLoweringMatt Arsenault2014-06-231-0/+13
| | | | llvm-svn: 211516
* R600/SI: Handle i64 sub.Matt Arsenault2014-06-231-1/+0
| | | | | | We can handle it the same way as add llvm-svn: 211514
* R600: Rename AMDIL fileMatt Arsenault2014-06-231-1/+1
| | | | llvm-svn: 211512
* R600: Use LowerSDIVREM for i64 node replaceJan Vesely2014-06-221-90/+0
| | | | | | | | v2: move div/rem node replacement to R600ISelLowering make lowerSDIVREM protected Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211478
* R600: Implement custom SDIVREM.Jan Vesely2014-06-221-4/+43
| | | | | | | | | | Instead of separate SDIV/SREM. SDIV used UDIV which in turn used UDIVREM anyway. SREM used SDIV(UDIV->UDIVREM)+MUL+SUB, using UDIVREM directly is more efficient. v2: Don't use all caps names Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211477
* R600/SI: Add a pattern for f32 ftruncTom Stellard2014-06-201-0/+2
| | | | llvm-svn: 211377
* R600: Expand vector flog2Tom Stellard2014-06-201-0/+1
| | | | llvm-svn: 211376
* R600: Expand vector fexp2Tom Stellard2014-06-201-0/+1
| | | | llvm-svn: 211375
* R600/SI: Add intrinsics for various math instructions.Matt Arsenault2014-06-191-2/+30
| | | | | | | | These will be used for custom lowering and for library implementations of various math functions, so it's useful to expose these as builtins. llvm-svn: 211247
* Use stdint macros for specifying size of constantsMatt Arsenault2014-06-181-2/+3
| | | | llvm-svn: 211231
* R600: Handle fnearbyintMatt Arsenault2014-06-181-0/+12
| | | | | | | | The difference from rint isn't really relevant here, so treat them as equivalent. OpenCL doesn't have nearbyint, so this is sort of pointless other than for completeness. llvm-svn: 211229
* Use LL suffix for literal that should be 64-bits.Matt Arsenault2014-06-181-1/+1
| | | | | | This hopefully fixes Windows llvm-svn: 211225
* R600: Expand vector fceilJan Vesely2014-06-181-0/+1
| | | | | | | | | Move fp64 fceil tests to fceil64.ll v2: rebase Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211194
* Work around ridiculous warning.Matt Arsenault2014-06-181-2/+5
| | | | | | Apparently C++ doesn't really have hex floating point constants. llvm-svn: 211192
* R600/SI: Add intrinsics for brev instructionsMatt Arsenault2014-06-181-0/+4
| | | | llvm-svn: 211187
* R600: Implement f64 ftrunc, ffloor and fceil.Matt Arsenault2014-06-181-0/+107
| | | | | | CI has instructions for these, so this fixes them for older hardware. llvm-svn: 211183
* R600: Custom lower f64 frint for pre-CIMatt Arsenault2014-06-181-0/+26
| | | | llvm-svn: 211182
* R600/SI: Match ctlz_zero_undefMatt Arsenault2014-06-171-0/+2
| | | | llvm-svn: 211115
* R600: Use LDS and vectors for private memoryTom Stellard2014-06-171-0/+1
| | | | llvm-svn: 211110
* SelectionDAG: Expand i64 = FP_TO_SINT i32Tom Stellard2014-06-171-0/+1
| | | | llvm-svn: 211108
* Fix copy paste errorMatt Arsenault2014-06-151-1/+1
| | | | llvm-svn: 211003
* R600: Remove a few more things from AMDILISelLoweringMatt Arsenault2014-06-151-19/+21
| | | | | | | Try to keep all the setOperationActions for integer ops together. llvm-svn: 211001
* R600: Fix assert on vector sdivMatt Arsenault2014-06-151-4/+4
| | | | llvm-svn: 211000
* R600: Move / cleanup more leftover AMDIL stuff.Matt Arsenault2014-06-151-5/+19
| | | | llvm-svn: 210998
* R600: Move division custom lowering out of AMDILISelLoweringMatt Arsenault2014-06-151-2/+246
| | | | llvm-svn: 210997
* R600: Report that integer division is expensive.Matt Arsenault2014-06-151-0/+7
| | | | | | Divides by weird constants now emit much better code. llvm-svn: 210995
* R600: Fix asserts related to constant initializersMatt Arsenault2014-06-141-5/+20
| | | | | | | | | | | This would assert if a constant address space was extern and therefore didn't have an initializer. If the initializer was undef, it would hit the unreachable unhandled initializer case. An extern global should never really occur since we don't have machine linking, but bugpoint likes to remove initializers. llvm-svn: 210967
* R600: Use address space enum instead of valueMatt Arsenault2014-06-141-6/+7
| | | | llvm-svn: 210966
* R600: Cleanup some old AMDIL stuff.Matt Arsenault2014-06-131-9/+31
| | | | | | | | | | | | Move / delete some of the more obviously wrong setOperationAction calls. Most of these are setting Expand for types that aren't legal which is the default anyway. Leave stuff that might require more thought on whether it's junk or not as it is. No functionality change. llvm-svn: 210922
* R600/SI: Fix selection error on i64 rotl / rotr.Matt Arsenault2014-06-131-3/+7
| | | | | | Evergreen is still broken due to missing shl_parts. llvm-svn: 210885
* R600: Mostly remove remaining AMDIL intrinsics.Matt Arsenault2014-06-121-11/+15
| | | | | | | | | Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. llvm-svn: 210827
* R600/SI: Use v_cvt_f32_ubyte* instructionsMatt Arsenault2014-06-111-1/+16
| | | | | | | This eliminates extra extract instructions when loading an i8 vector to a float vector. llvm-svn: 210666
* Try to fix the msvc build.Rafael Espindola2014-06-111-1/+2
| | | | llvm-svn: 210636
* Use cast instead of assert + dyn_castMatt Arsenault2014-06-111-3/+2
| | | | llvm-svn: 210628
* R600: Add helper functions.Matt Arsenault2014-06-111-0/+19
| | | | | | | Extract these from some of my other patches, since this is the only thing really making them dependent on each other. llvm-svn: 210627
* R600: Use BCNT_INT for evergreenMatt Arsenault2014-06-101-2/+6
| | | | llvm-svn: 210569
* R600/SI: Use bcnt instruction for ctpopMatt Arsenault2014-06-101-1/+11
| | | | llvm-svn: 210567
* R600: Handle fcopysignMatt Arsenault2014-06-101-0/+7
| | | | llvm-svn: 210564
* R600: Fix selection failure for vector bswapMatt Arsenault2014-06-091-0/+1
| | | | llvm-svn: 210475
* R600: Set all float vector expands in the same placeMatt Arsenault2014-06-011-5/+2
| | | | llvm-svn: 209988
* R600: Try to convert BFE back to standard bit ops when possible.Matt Arsenault2014-05-221-0/+21
| | | | | | | This allows existing DAG combines to work on them, and then we can re-match to BFE if necessary during instruction selection. llvm-svn: 209462
* R600: Add dag combine for BFEMatt Arsenault2014-05-221-0/+74
| | | | llvm-svn: 209461
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