| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 211757
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Now we need only one 64-bit pattern for stores.
llvm-svn: 211643
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R600 was using a clamped version of rsq, but SI was not. Add a
new rsq_clamped intrinsic and use them consistently.
It's unclear to me from the documentation what behavior
the R600 instructions have, so I assume they have the legacy behavior
described by the SI documents. For R600, use RECIPSQRT_IEEE
for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also
has RECIPSQRT_FF, which I'm not sure how it fits in here.
llvm-svn: 211637
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This corresponded to an amdil instruction which there is
a 2 instruction equivalent for.
llvm-svn: 211616
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The operand that must match one of the others does matter,
and implement selecting for it.
llvm-svn: 211523
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llvm-svn: 211519
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llvm-svn: 211518
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Add more tests for these.
llvm-svn: 211517
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llvm-svn: 211516
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We can handle it the same way as add
llvm-svn: 211514
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llvm-svn: 211512
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v2: move div/rem node replacement to R600ISelLowering
make lowerSDIVREM protected
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211478
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Instead of separate SDIV/SREM. SDIV used UDIV which in turn used UDIVREM anyway.
SREM used SDIV(UDIV->UDIVREM)+MUL+SUB, using UDIVREM directly is more efficient.
v2: Don't use all caps names
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211477
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llvm-svn: 211377
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llvm-svn: 211376
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llvm-svn: 211375
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These will be used for custom lowering and for library
implementations of various math functions, so it's useful
to expose these as builtins.
llvm-svn: 211247
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llvm-svn: 211231
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The difference from rint isn't really relevant here,
so treat them as equivalent. OpenCL doesn't have nearbyint,
so this is sort of pointless other than for completeness.
llvm-svn: 211229
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This hopefully fixes Windows
llvm-svn: 211225
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Move fp64 fceil tests to fceil64.ll
v2: rebase
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211194
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Apparently C++ doesn't really have hex floating point constants.
llvm-svn: 211192
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llvm-svn: 211187
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CI has instructions for these, so this fixes them for older hardware.
llvm-svn: 211183
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llvm-svn: 211182
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llvm-svn: 211115
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llvm-svn: 211110
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llvm-svn: 211108
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llvm-svn: 211003
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Try to keep all the setOperationActions for integer ops
together.
llvm-svn: 211001
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llvm-svn: 211000
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llvm-svn: 210998
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llvm-svn: 210997
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Divides by weird constants now emit much better code.
llvm-svn: 210995
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This would assert if a constant address space was extern
and therefore didn't have an initializer. If the initializer
was undef, it would hit the unreachable unhandled initializer case.
An extern global should never really occur since we don't have
machine linking, but bugpoint likes to remove initializers.
llvm-svn: 210967
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llvm-svn: 210966
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Move / delete some of the more obviously wrong
setOperationAction calls. Most of these are setting Expand
for types that aren't legal which is the default anyway.
Leave stuff that might require more thought on whether it's
junk or not as it is.
No functionality change.
llvm-svn: 210922
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Evergreen is still broken due to missing shl_parts.
llvm-svn: 210885
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Delete all unused ones, and add new AMDGPU named intrinsics for
the ones that are. Handle the old AMDIL names for comptability (although
remove their GCCBuiltin names) and add tests since there weren't any
for these before.
llvm-svn: 210827
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This eliminates extra extract instructions when loading an i8 vector to
a float vector.
llvm-svn: 210666
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llvm-svn: 210636
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llvm-svn: 210628
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Extract these from some of my other patches, since this
is the only thing really making them dependent on each other.
llvm-svn: 210627
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llvm-svn: 210569
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llvm-svn: 210567
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llvm-svn: 210564
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llvm-svn: 210475
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llvm-svn: 209988
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This allows existing DAG combines to work on them, and then
we can re-match to BFE if necessary during instruction selection.
llvm-svn: 209462
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llvm-svn: 209461
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