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path: root/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
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* [SelectionDAG] Allow targets to specify legality of extloads' resultAhmed Bougacha2015-01-081-13/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | type (in addition to the memory type). The *LoadExt* legalization handling used to only have one type, the memory type. This forced users to assume that as long as the extload for the memory type was declared legal, and the result type was legal, the whole extload was legal. However, this isn't always the case. For instance, on X86, with AVX, this is legal: v4i32 load, zext from v4i8 but this isn't: v4i64 load, zext from v4i8 Whereas v4i64 is (arguably) legal, even without AVX2. Note that the same thing was done a while ago for truncstores (r46140), but I assume no one needed it yet for extloads, so here we go. Calls to getLoadExtAction were changed to add the value type, found manually in the surrounding code. Calls to setLoadExtAction were mechanically changed, by wrapping the call in a loop, to match previous behavior. The loop iterates over the MVT subrange corresponding to the memory type (FP vectors, etc...). I also pulled neighboring setTruncStoreActions into some of the loops; those shouldn't make a difference, as the additional types are illegal. (e.g., i128->i1 truncstores on PPC.) No functional change intended. Differential Revision: http://reviews.llvm.org/D6532 llvm-svn: 225421
* R600/SI: Add class intrinsicMatt Arsenault2015-01-061-0/+5
| | | | llvm-svn: 225305
* R600: Remove outdated commentMatt Arsenault2014-12-191-4/+0
| | | | llvm-svn: 224648
* R600/SI: Only form min/max with 1 use.Matt Arsenault2014-12-191-1/+1
| | | | | | | If the condition is used for something else, this increases the number of instructions. llvm-svn: 224646
* R600: Fix min/max matching problems with unordered comparesMatt Arsenault2014-12-121-42/+43
| | | | | | | | The returned operand needs to be permuted for the unordered compares. Also fix incorrectly producing fmin_legacy / fmax_legacy for f64, which don't exist. llvm-svn: 224094
* Add target hook for whether it is profitable to reduce load widthsMatt Arsenault2014-12-121-0/+23
| | | | | | | | Add an option to disable optimization to shrink truncated larger type loads to smaller type loads. On SI this prevents using scalar load instructions in some cases, since there are no scalar extloads. llvm-svn: 224084
* R600/SI: Update instruction conversions for VIMarek Olsak2014-12-071-1/+19
| | | | | | | | | There are 3 changes: - Convert 32-bit S_LSHL/LSHR/ASHR to their V_*REV variants for VI - Lower RSQ_CLAMP for VI - Don't generate MIN/MAX_LEGACY on VI llvm-svn: 223604
* R600/SI: Use ZeroOrNegativeOneBooleanContentMatt Arsenault2014-11-261-0/+3
| | | | | | | | | | | | | | This sort of doesn't matter since the setcc type is i1, but this previously was using the default UndefinedBooleanContent. This makes it more consistent with R600. This enables more optimizations which typically give up on UndefinedBooleanContent. For example, there is already a special case target DAG combine for setcc + sext which can be eliminated in favor of what the generic DAG combiner can do if it assumes boolean values are sign extended. Since -1 is an inline immediate, using it is basically free and the backend already uses it when a boolean value is needed in a wider type. llvm-svn: 222850
* R600: Fix assert on copy of an i1 on pre-SIMatt Arsenault2014-11-231-1/+2
| | | | | | | i1 is not a legal type on Evergreen, so this combine proceeded and tried to produce a bitcast between i1 and i8. llvm-svn: 222630
* R600: Permute operands when selecting legacy min/maxMatt Arsenault2014-11-151-6/+9
| | | | | | | | | | This gets the correct NaN behavior based on the compare type the hardware uses. This now passes the new piglit test I have for this on SI. Add stricter tests for the operand order. llvm-svn: 222079
* R600: Fix 64-bit integer divisionTom Stellard2014-11-151-2/+2
| | | | | | | | This fixes a failure in one of the oclconform tests. Patch by: Jan Vesely llvm-svn: 222073
* R600: Factor i64 UDIVREM lowering into its own fuctionTom Stellard2014-11-151-0/+81
| | | | | | | | This is so it could potentially be used by SI. However, the current implementation does not always produce correct results, so the IntegerDivisionPass is being used instead. llvm-svn: 222072
* R600/SI: Combine min3/max3 instructionsMatt Arsenault2014-11-141-0/+6
| | | | llvm-svn: 222032
* R600/SI: Match integer min / max instructionsMatt Arsenault2014-11-141-21/+69
| | | | llvm-svn: 222015
* R600/SI: Fix fmin_legacy / fmax_legacy matching for SIMatt Arsenault2014-11-131-19/+50
| | | | | | select_cc is expanded on SI, so this was never matched. llvm-svn: 221941
* We can get the TLOF from the TargetMachine - so constructor no longer ↵Aditya Nandakumar2014-11-131-1/+1
| | | | | | requires TargetLoweringObjectFile to be passed. llvm-svn: 221926
* R600: Error on initializer for LDS.Matt Arsenault2014-11-131-2/+21
| | | | | | Also give a proper error for other address spaces. llvm-svn: 221917
* This patch changes the ownership of TLOF from TargetLoweringBase to ↵Aditya Nandakumar2014-11-131-1/+1
| | | | | | TargetMachine so that different subtargets could share the TLOF effectively llvm-svn: 221878
* Add minnum / maxnum codegenMatt Arsenault2014-10-211-0/+2
| | | | llvm-svn: 220342
* R600/SI: Add missing parameter to div_fmas intrinsicMatt Arsenault2014-10-211-0/+2
| | | | llvm-svn: 220338
* R600: Fix nonsensical implementation of computeKnownBits for BFEMatt Arsenault2014-10-161-5/+1
| | | | | | This was resulting in invalid simplifications of sdiv llvm-svn: 219953
* R600: Remove dead functionMatt Arsenault2014-10-161-12/+0
| | | | llvm-svn: 219879
* R600: Remove unnecessary part of computeKnownBitsForTargetNodeMatt Arsenault2014-10-151-5/+0
| | | | | | | Zero-width BFEs are combined away already, so there's no point in handling them. llvm-svn: 219868
* Move variable down to useMatt Arsenault2014-10-151-4/+4
| | | | llvm-svn: 219867
* R600: Fix miscompiles when BFE has multiple usesMatt Arsenault2014-10-151-7/+10
| | | | | | SimplifyDemandedBits would break the other uses of the operand. llvm-svn: 219819
* R600: Use existing variableMatt Arsenault2014-10-151-1/+1
| | | | llvm-svn: 219778
* R600: Remove outdated commentMatt Arsenault2014-10-151-3/+0
| | | | llvm-svn: 219777
* R600/SI: Custom lower f64 -> i64 conversionsMatt Arsenault2014-10-031-0/+53
| | | | llvm-svn: 219038
* R600: Custom lower [s|u]int_to_fp for i64 -> f64Matt Arsenault2014-10-031-2/+43
| | | | llvm-svn: 219037
* R600/SI: Fix ftrunc f64 conformance failures.Matt Arsenault2014-10-031-1/+1
| | | | | | Re-add the tests since they were deleted at some point llvm-svn: 219036
* R600/SI: Add a note about the order of the operands to div_scaleMatt Arsenault2014-09-261-0/+6
| | | | llvm-svn: 218534
* R600: Don't set BypassSlowDiv for 64-bit divisionTom Stellard2014-09-221-3/+0
| | | | | | | | | | | | | BypassSlowDiv is used by codegen prepare to insert a run-time check to see if the operands to a 64-bit division are really 32-bit values and if they are it will do 32-bit division instead. This is not useful for R600, which has predicated control flow since both the 32-bit and 64-bit paths will be executed in most cases. It also increases code size which can lead to more instruction cache misses. llvm-svn: 218252
* R600/SI: Use ISD::MUL instead of ISD::UMULO when lowering divisionTom Stellard2014-09-221-3/+3
| | | | | | | ISD::MUL and ISD:UMULO are the same except that UMULO sets an overflow bit. Since we aren't using the overflow bit, we should use ISD::MUL. llvm-svn: 218251
* R600: Better fix for bug 20982Matt Arsenault2014-09-191-6/+3
| | | | | | Just do the left shift as unsigned to avoid the UB. llvm-svn: 218092
* R600: Bug 20982 - Avoid undefined left shift of negative valueMatt Arsenault2014-09-181-3/+10
| | | | | | | I'm not sure what the hardware actually does, so don't bother trying to fold it for now. llvm-svn: 218057
* R600: Custom lower fremMatt Arsenault2014-09-101-0/+19
| | | | llvm-svn: 217553
* R600/SI: Use mad for fsub + fmulMatt Arsenault2014-08-291-0/+1
| | | | | | | We can use a negate source modifier to match this for fsub. llvm-svn: 216735
* name change: isPow2DivCheap -> isPow2SDivCheapSanjay Patel2014-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | isPow2DivCheap That name doesn't specify signed or unsigned. Lazy as I am, I eventually read the function and variable comments. It turns out that this is strictly about signed div. But I discovered that the comments are wrong: srl/add/sra is not the general sequence for signed integer division by power-of-2. We need one more 'sra': sra/srl/add/sra That's the sequence produced in DAGCombiner. The first 'sra' may be removed when dividing by exactly '2', but that's a special case. This patch corrects the comments, changes the name of the flag bit, and changes the name of the accessor methods. No functional change intended. Differential Revision: http://reviews.llvm.org/D5010 llvm-svn: 216237
* R600/SI: Use source modifiers for f64 fnegMatt Arsenault2014-08-151-1/+1
| | | | llvm-svn: 215748
* R600/SI: Use source modifier for f64 fabsMatt Arsenault2014-08-151-1/+1
| | | | llvm-svn: 215747
* R600/SI: Add intrinsic for ldexpMatt Arsenault2014-08-151-0/+5
| | | | llvm-svn: 215734
* R600: Use optimized 24bit path in udivremJan Vesely2014-08-121-17/+38
| | | | | | | | | v2: drop enum keyword use correct extension mode don't bother computing the sign in unsinged case Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 215462
* R600: Remove unused code.Jan Vesely2014-08-121-168/+0
| | | | | Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 215461
* R600: Use i24 optimized path for SREMJan Vesely2014-08-121-7/+27
| | | | | | | | | v2: add tests rename LowerSDIV24 to LowerSDIVREM24 handle the rem part in this function Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 215460
* R600: Disable FP exceptions.Matt Arsenault2014-08-091-0/+5
| | | | llvm-svn: 215277
* R600/SI: Avoid generating REGISTER_LOAD instructions.Tom Stellard2014-08-051-1/+2
| | | | | | | SI doesn't use REGISTER_LOAD anymore, but it was still hitting this code path for 8-bit and 16-bit private loads. llvm-svn: 214865
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-4/+4
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Use the known address space constant rather than checking itMatt Arsenault2014-08-041-1/+1
| | | | llvm-svn: 214729
* Revert "R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cpp"Tom Stellard2014-08-011-1/+37
| | | | | | | | This reverts commit r214566. I did not mean to commit this yet. llvm-svn: 214572
* R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cppTom Stellard2014-08-011-37/+1
| | | | | | | SI doesn't use REGISTER_LOAD anymore, but it was still hitting this code path for 8-bit and 16-bit private loads. llvm-svn: 214566
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