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* Make sure no loads resulting from load->switch DAGCombine are marked invariantLouis Gerbarg2014-07-311-3/+3
| | | | | | | | | | | | | | Currently when DAGCombine converts loads feeding a switch into a switch of addresses feeding a load the new load inherits the isInvariant flag of the left side. This is incorrect since invariant loads can be reordered in cases where it is illegal to reoarder normal loads. This patch adds an isInvariant parameter to getExtLoad() and updates all call sites to pass in the data if they have it or false if they don't. It also changes the DAGCombine to use that data to make the right decision when creating the new load. llvm-svn: 214449
* [SDAG] Enable the new assert for out-of-range result numbers inChandler Carruth2014-07-251-2/+2
| | | | | | | | | | | | | | | | SDValues, fixing the two bugs left in the regression suite. The key for both of these was the use a single value type rather than a VTList which caused an unintentionally single-result merge-value node. Fix this by getting the appropriate VTList in place. Doing this exposed that the comments in x86's code abouth how MUL_LOHI operands are handle is wrong. The bug with the use of out-of-range result numbers was hiding the bug about the order of operands here (as best i can tell). There are more places where the code appears to get this backwards still... llvm-svn: 213931
* R600: Add new functions for splitting vector loads and stores.Matt Arsenault2014-07-241-20/+129
| | | | | | These will be used in future patches and shouldn't change anything yet. llvm-svn: 213877
* R600: Fix LowerSDIV24Matt Arsenault2014-07-241-51/+50
| | | | | | | | | | Use ComputeNumSignBits instead of checking for i8 / i16 which only worked when AMDIL was lying about having legal i8 / i16. If an integer is known to fit in 24-bits, we can do division faster with float ops. llvm-svn: 213843
* R600/SI: Store constant initializer data in constant memoryTom Stellard2014-07-211-16/+1
| | | | | | | | | | | | This implements a solution for constant initializers suggested by Vadim Girlin, where we store the data after the shader code and then use the S_GETPC instruction to compute its address. This saves use the trouble of creating a new buffer for constant data and then having to pass the pointer to the kernel via user SGPRs or the input buffer. llvm-svn: 213530
* R600: support fpext/fptrunc operations to and from f16.Tim Northover2014-07-181-0/+4
| | | | llvm-svn: 213376
* R600: support f16 -> f64 conversion intrinsic.Tim Northover2014-07-181-0/+2
| | | | | | | | Unfortunately, we don't seem to have a direct truncation, but the extension can be legally split into two operations so we should support that. llvm-svn: 213357
* R600: Implement zero undef variants of ctlz/cttzJan Vesely2014-07-151-0/+6
| | | | | | | | | v2: use ffbh/l if available v3: Rebase on top of Matt's SI patches Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 213072
* R600: Add dag combine for copy of an illegal type.Matt Arsenault2014-07-151-1/+55
| | | | | | | | | This helps avoid redundant instructions to unpack, and repack the vectors. Ideally we could recognize that pattern and eliminate it. Currently v4i8 and other small element type vectors are scalarized, so this has the added bonus of avoiding that. llvm-svn: 213031
* R600: Implement float to long/ulongJan Vesely2014-07-101-1/+0
| | | | | | | | | | | | | | Use alg. from LegalizeDAG.cpp Move Expand setting to SIISellowering v2: Extend existing tests instead of creating new ones v3: use separate LowerFPTOSINT function v4: use TargetLowering::expandFP_TO_SINT add comment about using FP_TO_SINT for uints Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 212773
* R600: Fix mishandling of load / store chains.Matt Arsenault2014-07-071-11/+49
| | | | | | | | Fixes various bugs with reordering loads and stores. Scalarized vector loads weren't collecting the chains at all. llvm-svn: 212473
* R600: Add a comment that llvm.AMDGPU.trunc is a legacy intrinsicTom Stellard2014-07-021-1/+1
| | | | llvm-svn: 212218
* R600: Promote i64 loads to v2i32Tom Stellard2014-07-021-0/+3
| | | | llvm-svn: 212216
* R600: Fix crashes when an illegal type load or store is not handled.Matt Arsenault2014-07-021-2/+6
| | | | | | | I don't think anything hits this now, but will be exposed in future patches. llvm-svn: 212197
* R600: Move mul combine to separate functionMatt Arsenault2014-06-301-28/+33
| | | | llvm-svn: 212052
* R600: Move load/store ReplaceNodeResults to common code.Matt Arsenault2014-06-271-0/+14
| | | | | | Future patches will want to custom lower loads on SI. llvm-svn: 211848
* Silencing a warning about isZExtFree hiding an inherited virtual function. ↵Aaron Ballman2014-06-261-0/+4
| | | | | | No functional change intended. llvm-svn: 211783
* R600: Fix vector FMAMatt Arsenault2014-06-261-0/+1
| | | | llvm-svn: 211757
* R600: Promote i64 stores to v2i32Tom Stellard2014-06-241-0/+3
| | | | | | Now we need only one 64-bit pattern for stores. llvm-svn: 211643
* R600: Fix inconsistency in rsq instructions.Matt Arsenault2014-06-241-0/+8
| | | | | | | | | | | | | R600 was using a clamped version of rsq, but SI was not. Add a new rsq_clamped intrinsic and use them consistently. It's unclear to me from the documentation what behavior the R600 instructions have, so I assume they have the legacy behavior described by the SI documents. For R600, use RECIPSQRT_IEEE for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also has RECIPSQRT_FF, which I'm not sure how it fits in here. llvm-svn: 211637
* R600: Remove DIV_INFMatt Arsenault2014-06-241-2/+2
| | | | | | | This corresponded to an amdil instruction which there is a 2 instruction equivalent for. llvm-svn: 211616
* R600/SI: Fix div_scale intrinsic.Matt Arsenault2014-06-231-2/+14
| | | | | | | The operand that must match one of the others does matter, and implement selecting for it. llvm-svn: 211523
* R600: Remove AMDILISelLoweringMatt Arsenault2014-06-231-7/+0
| | | | llvm-svn: 211519
* R600: Select is not expensive.Matt Arsenault2014-06-231-0/+7
| | | | llvm-svn: 211518
* R600: Move add/sub with overflow out of AMDILISelLoweringMatt Arsenault2014-06-231-0/+4
| | | | | | Add more tests for these. llvm-svn: 211517
* R600: Move more out of AMDILISelLoweringMatt Arsenault2014-06-231-0/+13
| | | | llvm-svn: 211516
* R600/SI: Handle i64 sub.Matt Arsenault2014-06-231-1/+0
| | | | | | We can handle it the same way as add llvm-svn: 211514
* R600: Rename AMDIL fileMatt Arsenault2014-06-231-1/+1
| | | | llvm-svn: 211512
* R600: Use LowerSDIVREM for i64 node replaceJan Vesely2014-06-221-90/+0
| | | | | | | | v2: move div/rem node replacement to R600ISelLowering make lowerSDIVREM protected Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211478
* R600: Implement custom SDIVREM.Jan Vesely2014-06-221-4/+43
| | | | | | | | | | Instead of separate SDIV/SREM. SDIV used UDIV which in turn used UDIVREM anyway. SREM used SDIV(UDIV->UDIVREM)+MUL+SUB, using UDIVREM directly is more efficient. v2: Don't use all caps names Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211477
* R600/SI: Add a pattern for f32 ftruncTom Stellard2014-06-201-0/+2
| | | | llvm-svn: 211377
* R600: Expand vector flog2Tom Stellard2014-06-201-0/+1
| | | | llvm-svn: 211376
* R600: Expand vector fexp2Tom Stellard2014-06-201-0/+1
| | | | llvm-svn: 211375
* R600/SI: Add intrinsics for various math instructions.Matt Arsenault2014-06-191-2/+30
| | | | | | | | These will be used for custom lowering and for library implementations of various math functions, so it's useful to expose these as builtins. llvm-svn: 211247
* Use stdint macros for specifying size of constantsMatt Arsenault2014-06-181-2/+3
| | | | llvm-svn: 211231
* R600: Handle fnearbyintMatt Arsenault2014-06-181-0/+12
| | | | | | | | The difference from rint isn't really relevant here, so treat them as equivalent. OpenCL doesn't have nearbyint, so this is sort of pointless other than for completeness. llvm-svn: 211229
* Use LL suffix for literal that should be 64-bits.Matt Arsenault2014-06-181-1/+1
| | | | | | This hopefully fixes Windows llvm-svn: 211225
* R600: Expand vector fceilJan Vesely2014-06-181-0/+1
| | | | | | | | | Move fp64 fceil tests to fceil64.ll v2: rebase Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211194
* Work around ridiculous warning.Matt Arsenault2014-06-181-2/+5
| | | | | | Apparently C++ doesn't really have hex floating point constants. llvm-svn: 211192
* R600/SI: Add intrinsics for brev instructionsMatt Arsenault2014-06-181-0/+4
| | | | llvm-svn: 211187
* R600: Implement f64 ftrunc, ffloor and fceil.Matt Arsenault2014-06-181-0/+107
| | | | | | CI has instructions for these, so this fixes them for older hardware. llvm-svn: 211183
* R600: Custom lower f64 frint for pre-CIMatt Arsenault2014-06-181-0/+26
| | | | llvm-svn: 211182
* R600/SI: Match ctlz_zero_undefMatt Arsenault2014-06-171-0/+2
| | | | llvm-svn: 211115
* R600: Use LDS and vectors for private memoryTom Stellard2014-06-171-0/+1
| | | | llvm-svn: 211110
* SelectionDAG: Expand i64 = FP_TO_SINT i32Tom Stellard2014-06-171-0/+1
| | | | llvm-svn: 211108
* Fix copy paste errorMatt Arsenault2014-06-151-1/+1
| | | | llvm-svn: 211003
* R600: Remove a few more things from AMDILISelLoweringMatt Arsenault2014-06-151-19/+21
| | | | | | | Try to keep all the setOperationActions for integer ops together. llvm-svn: 211001
* R600: Fix assert on vector sdivMatt Arsenault2014-06-151-4/+4
| | | | llvm-svn: 211000
* R600: Move / cleanup more leftover AMDIL stuff.Matt Arsenault2014-06-151-5/+19
| | | | llvm-svn: 210998
* R600: Move division custom lowering out of AMDILISelLoweringMatt Arsenault2014-06-151-2/+246
| | | | llvm-svn: 210997
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