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path: root/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
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* R600: Add support for global vector stores with elements less than 32-bitsTom Stellard2013-08-161-0/+61
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188520
* R600: Add support for i16 and i8 global storesTom Stellard2013-08-161-0/+1
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188519
* R600/SI: Improve legalization of vector operationsTom Stellard2013-08-141-2/+47
| | | | | | This should fix hangs in the OpenCL piglit tests. llvm-svn: 188431
* R600/SI: Convert v16i8 resource descriptors to i128Tom Stellard2013-08-141-0/+6
| | | | | | | | | | | | | Now that compute support is better on SI, we can't continue using v16i8 for descriptors since this is also a legal type in OpenCL. This patch fixes numerous hangs with the piglit OpenCL test and since we now use a target specific DAG node for LOAD_CONSTANT with the correct MemOperandFlags, this should also fix: https://bugs.freedesktop.org/show_bug.cgi?id=66805 llvm-svn: 188429
* R600: Implement TargetLowering::getVectorIdxTy()Tom Stellard2013-08-051-0/+9
| | | | | | | We use MVT::i32 for the vector index type, because we use 32-bit operations to caculate offsets when dynamically indexing vectors. llvm-svn: 187749
* R600: Add 64-bit float load/store supportTom Stellard2013-08-011-0/+3
| | | | | | | | | | | | | | | | | * Added R600_Reg64 class * Added T#Index#.XY registers definition * Added v2i32 register reads from parameter and global space * Added f32 and i32 elements extraction from v2f32 and v2i32 * Added v2i32 -> v2f32 conversions Tom Stellard: - Mark vec2 operations as expand. The addition of a vec2 register class made them all legal. Patch by: Dmitry Cherkassov Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com> llvm-svn: 187582
* R600/SI: Expand vector fp <-> int conversionsTom Stellard2013-07-301-0/+4
| | | | llvm-svn: 187421
* DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)FreeTom Stellard2013-07-231-0/+14
| | | | | | | This commit also implements these functions for R600 and removes a test case that was relying on the buggy behavior. llvm-svn: 187007
* R600: Use the same compute kernel calling convention for all GPUsTom Stellard2013-07-231-0/+1
| | | | | | | | A side-effect of this is that now the compiler expects kernel arguments to be 4-byte aligned. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186916
* R600: Expand vector FNEGTom Stellard2013-07-231-0/+3
| | | | llvm-svn: 186913
* R600/SI: Add support for v2f32 loadsTom Stellard2013-07-181-0/+3
| | | | llvm-svn: 186615
* R600/SI: Add support for v2f32 storesTom Stellard2013-07-181-0/+3
| | | | llvm-svn: 186614
* R600: Expand VSELECT for all typesTom Stellard2013-07-181-0/+3
| | | | llvm-svn: 186613
* Make some arrays 'static const'Craig Topper2013-07-151-1/+1
| | | | llvm-svn: 186307
* Use llvm::array_lengthof to replace sizeof(array)/sizeof(array[0]).Craig Topper2013-07-151-1/+1
| | | | llvm-svn: 186301
* R600/SI: Add initial double precision support for SITom Stellard2013-07-121-0/+6
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186177
* R600/SI: Initial local memory supportMichel Danzer2013-07-101-3/+1
| | | | | | | Enough for the radeonsi driver to use it for calculating derivatives. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186012
* R600: Add local memory support via LDSTom Stellard2013-06-281-0/+23
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185162
* R600: Consolidate expansion of v2i32/v4i32 ops for EG/SIAaron Watry2013-06-251-0/+22
| | | | | | | | | | By default, we expand these operations for both EG and SI. Move the duplicated code into a common space for now. If the targets ever actually implement these operations as instructions, we can override that in the relevant target. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184848
* R600/SI: Add a calling convention for compute shadersTom Stellard2013-06-031-0/+2
| | | | llvm-svn: 183137
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-6/+6
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* Move passes from namespace llvm into anonymous namespaces. Sort includes ↵Benjamin Kramer2013-05-231-1/+1
| | | | | | while there. llvm-svn: 182594
* R600: Swap the legality of rotl and rotrTom Stellard2013-05-201-0/+3
| | | | | | The hardware supports rotr and not rotl. llvm-svn: 182285
* R600/SI: add mulhu/mulhs patternsChristian Konig2013-03-271-0/+2
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178126
* R600/SI: add proper formal parameter handling for SIChristian Konig2013-03-071-11/+9
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176623
* R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad patternVincent Lejeune2013-02-181-7/+3
| | | | llvm-svn: 175446
* R600: Support for indirect addressing v4Tom Stellard2013-02-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525
* R600: improve inputs/interpolation handlingTom Stellard2013-02-051-2/+0
| | | | | | | | | | | | | | | | Use one intrinsic for all sorts of interpolation. Use two separate unexpanded instructions to represent INTERP_XY and _ZW - this will allow to eliminate one part if it's not used. Track liveness of special interpolation regs instead of reserving them - this will allow to reuse those regs, lowering reg pressure. Patch By: Vadim Girlin v2[Vincent Lejeune]: Rebased against current llvm master Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174394
* R600: Add a CONST_ADDRESS node to model constant buf readTom Stellard2013-01-231-0/+1
| | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 173221
* Add R600 backendTom Stellard2012-12-111-0/+417
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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