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path: root/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
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* name change: isPow2DivCheap -> isPow2SDivCheapSanjay Patel2014-08-211-1/+1
* R600/SI: Use source modifiers for f64 fnegMatt Arsenault2014-08-151-1/+1
* R600/SI: Use source modifier for f64 fabsMatt Arsenault2014-08-151-1/+1
* R600/SI: Add intrinsic for ldexpMatt Arsenault2014-08-151-0/+5
* R600: Use optimized 24bit path in udivremJan Vesely2014-08-121-17/+38
* R600: Remove unused code.Jan Vesely2014-08-121-168/+0
* R600: Use i24 optimized path for SREMJan Vesely2014-08-121-7/+27
* R600: Disable FP exceptions.Matt Arsenault2014-08-091-0/+5
* R600/SI: Avoid generating REGISTER_LOAD instructions.Tom Stellard2014-08-051-1/+2
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-4/+4
* Use the known address space constant rather than checking itMatt Arsenault2014-08-041-1/+1
* Revert "R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cpp"Tom Stellard2014-08-011-1/+37
* R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cppTom Stellard2014-08-011-37/+1
* Make sure no loads resulting from load->switch DAGCombine are marked invariantLouis Gerbarg2014-07-311-3/+3
* [SDAG] Enable the new assert for out-of-range result numbers inChandler Carruth2014-07-251-2/+2
* R600: Add new functions for splitting vector loads and stores.Matt Arsenault2014-07-241-20/+129
* R600: Fix LowerSDIV24Matt Arsenault2014-07-241-51/+50
* R600/SI: Store constant initializer data in constant memoryTom Stellard2014-07-211-16/+1
* R600: support fpext/fptrunc operations to and from f16.Tim Northover2014-07-181-0/+4
* R600: support f16 -> f64 conversion intrinsic.Tim Northover2014-07-181-0/+2
* R600: Implement zero undef variants of ctlz/cttzJan Vesely2014-07-151-0/+6
* R600: Add dag combine for copy of an illegal type.Matt Arsenault2014-07-151-1/+55
* R600: Implement float to long/ulongJan Vesely2014-07-101-1/+0
* R600: Fix mishandling of load / store chains.Matt Arsenault2014-07-071-11/+49
* R600: Add a comment that llvm.AMDGPU.trunc is a legacy intrinsicTom Stellard2014-07-021-1/+1
* R600: Promote i64 loads to v2i32Tom Stellard2014-07-021-0/+3
* R600: Fix crashes when an illegal type load or store is not handled.Matt Arsenault2014-07-021-2/+6
* R600: Move mul combine to separate functionMatt Arsenault2014-06-301-28/+33
* R600: Move load/store ReplaceNodeResults to common code.Matt Arsenault2014-06-271-0/+14
* Silencing a warning about isZExtFree hiding an inherited virtual function. No...Aaron Ballman2014-06-261-0/+4
* R600: Fix vector FMAMatt Arsenault2014-06-261-0/+1
* R600: Promote i64 stores to v2i32Tom Stellard2014-06-241-0/+3
* R600: Fix inconsistency in rsq instructions.Matt Arsenault2014-06-241-0/+8
* R600: Remove DIV_INFMatt Arsenault2014-06-241-2/+2
* R600/SI: Fix div_scale intrinsic.Matt Arsenault2014-06-231-2/+14
* R600: Remove AMDILISelLoweringMatt Arsenault2014-06-231-7/+0
* R600: Select is not expensive.Matt Arsenault2014-06-231-0/+7
* R600: Move add/sub with overflow out of AMDILISelLoweringMatt Arsenault2014-06-231-0/+4
* R600: Move more out of AMDILISelLoweringMatt Arsenault2014-06-231-0/+13
* R600/SI: Handle i64 sub.Matt Arsenault2014-06-231-1/+0
* R600: Rename AMDIL fileMatt Arsenault2014-06-231-1/+1
* R600: Use LowerSDIVREM for i64 node replaceJan Vesely2014-06-221-90/+0
* R600: Implement custom SDIVREM.Jan Vesely2014-06-221-4/+43
* R600/SI: Add a pattern for f32 ftruncTom Stellard2014-06-201-0/+2
* R600: Expand vector flog2Tom Stellard2014-06-201-0/+1
* R600: Expand vector fexp2Tom Stellard2014-06-201-0/+1
* R600/SI: Add intrinsics for various math instructions.Matt Arsenault2014-06-191-2/+30
* Use stdint macros for specifying size of constantsMatt Arsenault2014-06-181-2/+3
* R600: Handle fnearbyintMatt Arsenault2014-06-181-0/+12
* Use LL suffix for literal that should be 64-bits.Matt Arsenault2014-06-181-1/+1
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