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* R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0Tom Stellard2014-05-151-5/+6
| | | | llvm-svn: 208886
* R600/SI: Only select SALU instructions in the entry or exit blockTom Stellard2014-04-291-0/+15
| | | | | | | | SALU instructions ignore control flow, so it is not always safe to use them within branches. This is a partial solution to this problem until we can come up with something better. llvm-svn: 207590
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-3/+3
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition llvm-svn: 207503
* Convert SelectionDAG::SelectNodeTo to use ArrayRef.Craig Topper2014-04-271-3/+3
| | | | llvm-svn: 207377
* R600: Minor cleanups.Matt Arsenault2014-04-181-55/+50
| | | | | | Fix indentation, better line wrapping, unused includes. llvm-svn: 206562
* R600/SI: Try to use scalar BFE.Matt Arsenault2014-04-181-5/+43
| | | | | | | | Use scalar BFE with constant shift and offset when possible. This is complicated by the fact that the scalar version packs the two operands of the vector version into one. llvm-svn: 206558
* R600/SI: Use SReg_64 instead of VSrc_64 when selecting BUILD_PAIRTom Stellard2014-04-181-1/+1
| | | | llvm-svn: 206541
* Break PseudoSourceValue out of the Value hierarchy. It is now the root of ↵Nick Lewycky2014-04-151-22/+35
| | | | | | its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't). Anything that needs to use either a PseudoSourceValue* and Value* is strongly encouraged to use a MachinePointerInfo instead. llvm-svn: 206255
* R600: Match 24-bit arithmetic patterns in a Target DAGCombineTom Stellard2014-04-071-46/+0
| | | | | | | | | | | | | | | | | Moving these patterns from TableGen files to PerformDAGCombine() should allow us to generate better code by eliminating unnecessary shifts and extensions earlier. This also fixes a bug where the MAD pattern was calling SimplifyDemandedBits with a 24-bit mask on the first operand even when the full pattern wasn't being matched. This occasionally resulted in some instructions being incorrectly deleted from the program. v2: - Fix bug with 64-bit mul llvm-svn: 205731
* R600: Replace dyn_cast + assert with castTom Stellard2014-04-071-2/+1
| | | | llvm-svn: 205730
* R600/SI: Lower 64-bit immediates using REG_SEQUENCETom Stellard2014-04-031-0/+38
| | | | llvm-svn: 205561
* [Modules] Move ValueMap to the IR library. While this class does notChandler Carruth2014-03-041-1/+1
| | | | | | | | | | | | directly care about the Value class (it is templated so that the key can be any arbitrary Value subclass), it is in fact concretely tied to the Value class through the ValueHandle's CallbackVH interface which relies on the key type being some Value subclass to establish the value handle chain. Ironically, the unittest is already in the right library. llvm-svn: 202824
* R600/SI: Custom select 64-bit ADDTom Stellard2014-02-251-0/+48
| | | | llvm-svn: 202194
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-0/+34
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* ISelDAG: spot chain cycles involving MachineNodesTim Northover2013-09-221-0/+1
| | | | | | | | | | | | | | | | | Previously, the DAGISel function WalkChainUsers was spotting that it had entered already-selected territory by whether a node was a MachineNode (amongst other things). Since it's fairly common practice to insert MachineNodes during ISelLowering, this was not the correct check. Looking around, it seems that other nodes get their NodeId set to -1 upon selection, so this makes sure the same thing happens to all MachineNodes and uses that characteristic to determine whether we should stop looking for a loop during selection. This should fix PR15840. llvm-svn: 191165
* R600: Move clamp handling code to R600IselLowering.cppVincent Lejeune2013-09-121-33/+1
| | | | llvm-svn: 190645
* R600: Move code handling literal folding into R600ISelLowering.Vincent Lejeune2013-09-121-105/+0
| | | | llvm-svn: 190644
* R600: Move fabs/fneg/sel folding logic into PostProcessIselVincent Lejeune2013-09-121-245/+17
| | | | | | | This move makes possible to correctly handle multiples instructions from a single pattern. llvm-svn: 190643
* Mark an unreachable code path with llvm_unreachable. Pacifies GCC.Benjamin Kramer2013-08-311-0/+1
| | | | llvm-svn: 189726
* R600: Enable folding of inline literals into REQ_SEQUENCE instructionsTom Stellard2013-08-161-17/+20
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188517
* Tentative fix for global-buffer-overflow caused by r188426. Found by ↵Alexey Samsonov2013-08-151-1/+4
| | | | | | AddressSanitizer llvm-svn: 188448
* R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2Tom Stellard2013-08-141-19/+69
| | | | | | | | | | | | Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG instructions should make it easier for the register allocator to coalasce unnecessary copies. v2: - Use an SGPR register class if all the operands of BUILD_VECTOR are SGPRs. llvm-svn: 188427
* R600/SI: Choose the correct MOV instruction for copying immediatesTom Stellard2013-08-141-0/+29
| | | | | | | | The instruction selector will now try to infer the destination register so it can decided whether to use V_MOV_B32 or S_MOV_B32 when copying immediates. llvm-svn: 188426
* R600/SI: Use VSrc_* register classes as the default classes for typesTom Stellard2013-08-061-23/+1
| | | | | | | | | | | | | | | | | Since the VSrc_* register classes contain both VGPRs and SGPRs, copies that used be emitted by isel like this: SGPR = COPY VGPR Will now be emitted like this: VSrC = COPY VGPR This patch also adds a pass that tries to identify and fix situations where a VGPR to SGPR copy may occur. Hopefully, these changes will make it impossible for the compiler to generate illegal VGPR to SGPR copies. llvm-svn: 187831
* R600: Add 64-bit float load/store supportTom Stellard2013-08-011-1/+8
| | | | | | | | | | | | | | | | | * Added R600_Reg64 class * Added T#Index#.XY registers definition * Added v2i32 register reads from parameter and global space * Added f32 and i32 elements extraction from v2f32 and v2i32 * Added v2i32 -> v2f32 conversions Tom Stellard: - Mark vec2 operations as expand. The addition of a vec2 register class made them all legal. Patch by: Dmitry Cherkassov Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com> llvm-svn: 187582
* R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS loads when necessaryTom Stellard2013-07-231-0/+7
| | | | | | | | | | These are really the same address space in hardware. The only difference is that CONSTANT_ADDRESS uses a special cache for faster access. When we are unable to use the constant kcache for some reason (e.g. smaller types or lack of indirect addressing) then the instruction selector must use GLOBAL_ADDRESS loads instead. llvm-svn: 187006
* R600: Add support for 24-bit MUL instructionsTom Stellard2013-07-231-1/+49
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186922
* R600: Rename AMDILISelDAGToDAG.cpp -> AMDGPUISelDAGToDAG.cppTom Stellard2013-07-231-0/+789
Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186920
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