bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fix typo	Matt Arsenault	2014-06-14	1	-1/+1
\| \| \| \|	llvm-svn: 210968
*	[C++] Use 'nullptr'. Target edition.	Craig Topper	2014-04-25	1	-1/+1
\| \| \| \|	llvm-svn: 207197
*	R600: Take alignment into account when calculating the stack offset	Tom Stellard	2014-01-22	1	-4/+11
\| \| \| \|	llvm-svn: 199826
*	R600: Begin private memory at the second GPR.	Tom Stellard	2014-01-22	1	-1/+4
\| \| \| \| \| \| \|	This way private memory does not over-write work group information stored in GPRs 0 and 1. llvm-svn: 199824
*	R600: Fix calculation of stack offset in AMDGPUFrameLowering	Tom Stellard	2013-06-07	1	-21/+2
\| \| \| \| \| \| \| \| \|	We weren't computing structure size correctly and we were relying on the original alloca instruction to compute the offset, which isn't always reliable. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183568
*	R600: Support for indirect addressing v4	Tom Stellard	2013-02-06	1	-0/+122
	Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525