summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/R600/AMDGPUAsmPrinter.cpp
Commit message (Collapse)AuthorAgeFilesLines
* R600/SI: Remove VReg_32 register classTom Stellard2015-01-071-1/+1
| | | | | | | | | | | Use VGPR_32 register class instead. These two register classes were identical and having separate classes was causing SIInstrInfo::isLegalOperands() to be overly conservative in some cases. This change is necessary to prevent future paches from missing a folding opportunity in fneg-fabs.ll. llvm-svn: 225382
* R600/SI: Add a stub GCNTargetMachineTom Stellard2015-01-061-0/+1
| | | | | | | | | | | | This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
* R600/SI: Remove MachineFunction dump from AsmPrinterTom Stellard2015-01-061-17/+12
| | | | | | | The dump was dependent on a feature string, which meant that it couldn't be disabled or enable on a per compile basis. llvm-svn: 225275
* Silencing a 32-bit implicit conversion warning in MSVC; NFC.Aaron Ballman2014-12-031-1/+1
| | | | llvm-svn: 223237
* R600/SI: Emit amd_kernel_code_t header for AMDGPU environmentTom Stellard2014-12-021-1/+114
| | | | llvm-svn: 223160
* R600/SI: Move more information into SIProgramInfo structTom Stellard2014-12-021-45/+51
| | | | llvm-svn: 223154
* R600/SI: Refactor AMDGPUAsmPrinter::EmitProgramInfoSI()Tom Stellard2014-12-021-9/+11
| | | | llvm-svn: 223144
* R600: Align functions to 256 bytesTom Stellard2014-10-031-0/+4
| | | | llvm-svn: 219002
* R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol ↵Tom Stellard2014-10-011-1/+1
| | | | | | table llvm-svn: 218776
* R600/SI: Implement VGPR register spilling for compute at -O0 v3Tom Stellard2014-09-241-1/+5
| | | | | | | | | | | | | | VGPRs are spilled to LDS. This still needs more testing, but we need to at least enable it at -O0, because the fast register allocator spills all registers that are live at the end of blocks and without this some future commits will break the flat-address-space.ll test. v2: Only calculate thread id once v3: Move insertion of spill instructions to SIRegisterInfo::eliminateFrameIndex() llvm-svn: 218348
* R600/SI: Fix config value for number of gprsTom Stellard2014-09-191-4/+7
| | | | | | | | | | | | | | In r217636, the value stored in KernelInfo.Num[VS]GPRSs was changed from the highest GPR index used to the number of gprs in order to be consistent with the name of the variable. The code writing the config values still assumed that the value in this variable was the highest GPR index used, which caused the compiler to over report the number of GPRs being used. https://bugs.freedesktop.org/show_bug.cgi?id=84089 llvm-svn: 218150
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-151-0/+14
| | | | llvm-svn: 217777
* R600/SI: Fix off by 1 error in used register countMatt Arsenault2014-09-111-2/+4
| | | | | | | The register numbers start at 0, so if only 1 register was used, this was reported as 0. llvm-svn: 217636
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-4/+4
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* R600/SI: Use scratch memory for large private arraysTom Stellard2014-07-211-1/+23
| | | | llvm-svn: 213551
* R600/SI: Store constant initializer data in constant memoryTom Stellard2014-07-211-0/+10
| | | | | | | | | | | | This implements a solution for constant initializers suggested by Vadim Girlin, where we store the data after the shader code and then use the S_GETPC instruction to compute its address. This saves use the trouble of creating a new buffer for constant data and then having to pass the pointer to the kernel via user SGPRs or the input buffer. llvm-svn: 213530
* R600: Add denormal handling subtarget features.Matt Arsenault2014-07-141-3/+12
| | | | llvm-svn: 213018
* R600/SI: Default to no single precision denormals.Matt Arsenault2014-07-141-1/+9
| | | | llvm-svn: 213017
* R600: Use range for and fix missing consts.Matt Arsenault2014-07-131-25/+16
| | | | llvm-svn: 212897
* R600: Make ShaderType privateMatt Arsenault2014-07-131-7/+6
| | | | llvm-svn: 212896
* R600/SI: Add FP mode bits to binary.Matt Arsenault2014-06-261-10/+59
| | | | | | | | The default rounding mode to initialize the mode register needs to be reported to the runtime. Fill in other bits a kernel may be interested in setting for future use. llvm-svn: 211791
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-0/+1
| | | | llvm-svn: 210869
* R600/SI: Print code size along with used registersMatt Arsenault2014-04-151-12/+13
| | | | llvm-svn: 206336
* R600/SI: Use correct dest register class for V_READFIRSTLANE_B32Tom Stellard2014-03-171-1/+2
| | | | | | | | | | | | This instructions writes to an 32-bit SGPR. This change required adding the 32-bit VCC_LO and VCC_HI registers, because the full VCC register is 64 bits. This fixes verifier errors on several of the indirect addressing piglit tests. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 204055
* Remove MCPureStreamer.Rafael Espindola2014-02-271-2/+0
| | | | | | | We moved MCJIT to use native object formats a long time ago and R600 now uses ELF, so it was dead. llvm-svn: 202408
* Remove the last hasRawTextSupport call from R600.Rafael Espindola2014-01-311-2/+1
| | | | | | | | There is nothing wrong with printing the disassembly section when printing text. An hypothetical assembler would then produce a .o just like our direct object emission produces. llvm-svn: 200583
* Replace another use with hasRawTextSupport+EmitRawText with emitRawComment.Rafael Espindola2014-01-311-2/+2
| | | | llvm-svn: 200582
* Use emitRawComment to avoid a call to hasRawTextSupport.Rafael Espindola2014-01-311-3/+1
| | | | llvm-svn: 200581
* Add back spaces I missed in the conversion to emitRawComments.Rafael Espindola2014-01-271-3/+3
| | | | | | Sorry about that. llvm-svn: 200171
* Use emitRawComment instead of EmitRawText.Rafael Espindola2014-01-271-4/+5
| | | | llvm-svn: 200170
* R600: Add stack size to .AMDGPUcsdata sectionTom Stellard2014-01-221-4/+10
| | | | | reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199837
* Move declaration of variables down to first use.Matt Arsenault2014-01-081-6/+4
| | | | llvm-svn: 198794
* Use llvm_unreachable instead of assert(0)Matt Arsenault2013-12-101-1/+1
| | | | llvm-svn: 196971
* R600/SI: Add comments for number of used registers.Matt Arsenault2013-12-051-9/+41
| | | | llvm-svn: 196467
* Indentation fixesMatt Arsenault2013-11-141-1/+1
| | | | llvm-svn: 194688
* R600/SI: Add compute support for CI v2Tom Stellard2013-10-291-2/+14
| | | | | | | | v2: - Fix LDS size calculation Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 193621
* R600/SI: Use S_LOAD_DWORD instructions for v8i32 and v16i32Tom Stellard2013-10-231-0/+3
| | | | llvm-svn: 193212
* R600/SI: Don't assert on SCC usageMatt Arsenault2013-10-221-0/+2
| | | | llvm-svn: 193198
* R600: Store disassembly in a special ELF section when feature +DumpCode is ↵Tom Stellard2013-10-121-8/+36
| | | | | | | | | enabled. Patch by: Jay Cornwall Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 192523
* R600/SI: Initial local memory supportMichel Danzer2013-07-101-0/+7
| | | | | | | Enough for the radeonsi driver to use it for calculating derivatives. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186012
* R600: Add local memory support via LDSTom Stellard2013-06-281-0/+6
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185162
* R600: Rework subtarget info and remove AMDILDevice classesTom Stellard2013-06-071-2/+2
| | | | | | | | This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
* Move passes from namespace llvm into anonymous namespaces. Sort includes ↵Benjamin Kramer2013-05-231-3/+3
| | | | | | while there. llvm-svn: 182594
* R600: Emit config values in register / value pairsTom Stellard2013-05-061-3/+29
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181228
* R600: config section now reports use of killgtVincent Lejeune2013-04-301-0/+4
| | | | llvm-svn: 180751
* R600: Use SHT_PROGBITS for the .AMDGPU.config sectionTom Stellard2013-04-241-1/+1
| | | | | | | | The libelf implementation that is distributed here: http://www.mr511.de/software/english.html will not parse sections that are marked SHT_NULL. llvm-svn: 180230
* R600: Use .AMDGPU.config section to emit stacksizeVincent Lejeune2013-04-231-0/+3
| | | | llvm-svn: 180124
* R600: Emit used GPRs countVincent Lejeune2013-04-171-7/+39
| | | | llvm-svn: 179684
* R600/SI: Emit config values in register value pairs.Tom Stellard2013-04-151-3/+16
| | | | | | | | Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. llvm-svn: 179546
* R600/SI: Emit configuration value in the .AMDGPU.config ELF sectionTom Stellard2013-04-151-1/+9
| | | | llvm-svn: 179545
OpenPOWER on IntegriCloud