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* [PowerPC] Manually schedule the prologue and epilogueStefan Pintilie2018-01-091-6/+62
* [PowerPC] Can not assume an intrinsic argument is a simple type.Sean Fertile2018-01-091-6/+7
* Revert "[PowerPC] Manually schedule the prologue and epilogue"Stefan Pintilie2018-01-091-65/+6
* [PowerPC] Manually schedule the prologue and epilogueStefan Pintilie2018-01-081-6/+65
* [PowerPC] Add an ISD::TRUNCATE to the legalization for ppc_is_decremented_ctr...Craig Topper2018-01-071-1/+1
* Thread MCSubtargetInfo through Target::createMCAsmBackendAlex Bradbury2018-01-032-3/+6
* [PowerPC] fix a bug in TCO eligibility checkHiroshi Inoue2017-12-301-6/+29
* [PowerPC] Fix for PR35688 - handle out-of-range values for r+r to r+i conversionNemanja Ivanovic2017-12-294-23/+69
* (Re-landing) Expose a TargetMachine::getTargetTransformInfo functionSanjoy Das2017-12-222-5/+4
* [PowerPC] Fix parest build failure in SPEC2017.Tony Jiang2017-12-211-5/+6
* Revert "Expose a TargetMachine::getTargetTransformInfo function"Sanjoy Das2017-12-212-4/+5
* Expose a TargetMachine::getTargetTransformInfo functionSanjoy Das2017-12-212-5/+4
* [PowerPC] Added an assert to make sure that the MBBI iterator is valid.Stefan Pintilie2017-12-201-3/+3
* [PowerPC] fix a bug in redundant compare eliminationHiroshi Inoue2017-12-201-5/+13
* [PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.Benjamin Kramer2017-12-181-1/+1
* [PPC] Disable reg+reg to reg+imm transformation.Benjamin Kramer2017-12-181-1/+1
* [PowerPC, AsmParser] Enable the mnemonic spell correctorHal Finkel2017-12-161-2/+15
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-1515-36/+36
* Fix the second build bot break introduced by r320791.Nemanja Ivanovic2017-12-151-0/+7
* Fix code causing fallthrough warnings in the PPC back end.Nemanja Ivanovic2017-12-154-1/+7
* Fix the build bot break introduced by r320791.Nemanja Ivanovic2017-12-151-1/+6
* [PowerPC] Convert r+r instructions to r+i (pre and post RA)Nemanja Ivanovic2017-12-159-48/+1041
* Disabling r312514 as it causes miscompiles that show up on bootstrapNemanja Ivanovic2017-12-151-1/+1
* TLI: Allow using PSV for intrinsic mem operandsMatt Arsenault2017-12-142-0/+2
* DAG: Expose all MMO flags in getTgtMemIntrinsicMatt Arsenault2017-12-141-14/+6
* [CodeGen] Print global addresses as @foo in both MIR and debug outputFrancis Visoiu Mistrih2017-12-143-24/+24
* Fix link failure on one build bot introduced by r320584.Nemanja Ivanovic2017-12-131-1/+3
* [PowerPC] MachineSSA pass to reduce the number of CR-logical operationsNemanja Ivanovic2017-12-135-0/+740
* [Targets] Don't automatically include the scheduler class enum from *GenInstr...Craig Topper2017-12-131-0/+1
* Rename LiveIntervalAnalysis.h to LiveIntervals.hMatthias Braun2017-12-133-3/+3
* [PowerPC] Add branch flag on asm parser-only branch instructionsNemanja Ivanovic2017-12-121-1/+1
* [PowerPC] Follow-up to r318436 to get the missed CSE opportunitiesNemanja Ivanovic2017-12-121-1/+65
* [PowerPC] Partially enable the ISEL expansion pass.Tony Jiang2017-12-111-21/+64
* [PowerPC] Sign-extend negative constant storesNemanja Ivanovic2017-12-111-2/+6
* PowerPC: support external pid instructions in MC layer.Tim Northover2017-12-101-0/+57
* Temporarily revert "[PowerPC] Allow tail calls of fastcc functions from C Cal...Eric Christopher2017-12-071-10/+5
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-075-29/+29
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-047-47/+51
* Follow-up to r319434 to turn the pass on by defaultNemanja Ivanovic2017-12-011-1/+1
* [PowerPC] Recommit r314244 with refactoring and off by defaultNemanja Ivanovic2017-11-301-0/+1236
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-304-45/+45
* First step towards more human-friendly PPC assembler output:Joerg Sonnenberger2017-11-293-32/+74
* [PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended.Sean Fertile2017-11-291-3/+31
* [PowerPC] Allow tail calls of fastcc functions from C CallingConv functions.Sean Fertile2017-11-281-5/+10
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-288-72/+72
* [PowerPC] Remove redundant TOC savesZaara Syeda2017-11-273-2/+87
* [Power9] Improvements to vector extract with variable index exploitationZaara Syeda2017-11-271-22/+174
* [PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.Tony Jiang2017-11-205-46/+158
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-1715-18/+18
* [PPC] Change i32 constant in store instruction to i64Guozhi Wei2017-11-161-1/+16
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