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* Split the object streamer callback in one per file format.Rafael Espindola2015-03-191-18/+11
| | | | | | | | | | | | | There are two main advantages to doing this * Targets that only need to handle one of the formats specially don't have to worry about the others. For example, x86 now only registers a constructor for the COFF streamer. * Changes to the arguments passed to one format constructor will not impact the other formats. llvm-svn: 232699
* two or more, use a for.Rafael Espindola2015-03-181-58/+30
| | | | llvm-svn: 232688
* [PowerPC] Correct typo in PPCInstrAltivec.tdBill Schmidt2015-03-181-1/+1
| | | | llvm-svn: 232681
* Centralize the handling of unique ids for temporary labels.Rafael Espindola2015-03-171-3/+2
| | | | | | | | | | | | | | | | Before this patch code wanting to create temporary labels for a given entity (function, cu, exception range, etc) had to keep its own counter to have stable symbol names. createTempSymbol would still add a suffix to make sure a new symbol was always returned, but it kept a single counter. Because of that, if we were to use just createTempSymbol("cu_begin"), the label could change from cu_begin42 to cu_begin43 because some other code started using temporary labels. Simplify this by just keeping one counter per prefix and removing the various specialized counters. llvm-svn: 232535
* Add assertion to detect invalid registers in the PowerPC MC instruction ↵Samuel Antao2015-03-171-0/+3
| | | | | | | | lowering. We have observed that noreg was being generated due to a bug in FastIsel and was not being detected during emission. It happens that in the Asm emission there is an assertion that detects this in getRegisterName() from the tbl-generated file PPCGenAsmWriter.inc. However, when emitting an Obj file, invalid registers can be emitted given that no check are made in getBinaryCodeFromInstr() from PPCGenMCCodeEmitter.inc. In order to cover all cases this adds an assertion for reg operands in LowerPPCMachineInstrToMCInst. llvm-svn: 232525
* Fix R0 use in PowerPC VSX store for FastIsel.Samuel Antao2015-03-171-2/+12
| | | | | | The VSX stores are sometimes generated with a undefined index register, causing %noreg to be used and R0 to be emitted later on. The semantics of the VSX store (e.g. stdsdx) requires R0 to be used as base if we want zero to be used in the computation of the effective address instead of the content of R0. This patch checks if no index register was generated and forces R0 to be used as base address. llvm-svn: 232486
* Use createTempSymbol to avoid collisions instead of an ad hoc method.Rafael Espindola2015-03-171-10/+2
| | | | llvm-svn: 232483
* Fix r232466 by adding 'i' to the mappings for inline assembly memory ↵Daniel Sanders2015-03-171-0/+1
| | | | | | | | | constraints. It's not completely clear why 'i' has historically been treated as a memory constraint. According to the documentation, it represents a constant immediate. llvm-svn: 232470
* [ppc] Distinguish the 'es', 'o', 'm', 'Q', 'Z', and 'Zy' inline assembly ↵Daniel Sanders2015-03-172-14/+36
| | | | | | | | | | | | | | | | | | | | | | | memory constraints. Summary: But still handle them the same way since I don't know how they differ on this target. Of these, 'es', and 'Q' do not have backend tests but are accepted by clang. No functional change intended. Depends on D8173. Reviewers: hfinkel Reviewed By: hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8213 llvm-svn: 232466
* Pass in a "const Triple &T" instead of a raw StringRef.Rafael Espindola2015-03-161-2/+2
| | | | llvm-svn: 232429
* Remove unused argument. NFC.Rafael Espindola2015-03-161-3/+3
| | | | llvm-svn: 232428
* There is only one Asm streamer, there is no need for targets to register it.Rafael Espindola2015-03-161-13/+11
| | | | | | | Instead, have the targets register a TargetStreamer to be use with the asm streamer (if any). llvm-svn: 232423
* Fix uses of reserved identifiers starting with an underscore followed by an ↵David Blaikie2015-03-162-6/+5
| | | | | | | | | uppercase letter This covers essentially all of llvm's headers and libs. One or two weird cases I wasn't sure were worth/appropriate to fix. llvm-svn: 232394
* Make each target map all inline assembly memory constraints to ↵Daniel Sanders2015-03-161-0/+6
| | | | | | | | | | | | | | | | | | | InlineAsm::Constraint_m. NFC. Summary: This is instead of doing this in target independent code and is the last non-functional change before targets begin to distinguish between different memory constraints when selecting code for the ISD::INLINEASM node. Next, each target will individually move away from the idea that all memory constraints behave like 'm'. Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8173 llvm-svn: 232373
* [opaque pointer type] gep API migrationDavid Blaikie2015-03-141-5/+6
| | | | llvm-svn: 232279
* Recommit r232027 with PR22883 fixed: Add infrastructure for support of ↵Daniel Sanders2015-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | multiple memory constraints. The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. PR22883 was caused the matching operands copying the whole of the operand flags for the matched operand. This included the constraint id which needed to be replaced with the operand number. This has been fixed with a conversion function. Following on from this, matching operands also used the operand number as the constraint id. This has been fixed by looking up the matched operand and taking it from there. llvm-svn: 232165
* Revert "r232027 - Add infrastructure for support of multiple memory constraints"Hal Finkel2015-03-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This (r232027) has caused PR22883; so it seems those bits might be used by something else after all. Reverting until we can figure out what else to do. Original commit message: The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. llvm-svn: 232093
* Add infrastructure for support of multiple memory constraints.Daniel Sanders2015-03-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. Reviewers: hfinkel Reviewed By: hfinkel Subscribers: hfinkel, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8171 llvm-svn: 232027
* Remove some unnecessary forward declarations and put a couple moreEric Christopher2015-03-122-5/+1
| | | | | | where they're supposed to reside. llvm-svn: 232014
* Remove the need to cache the subtarget in the PowerPC TargetRegisterInfoEric Christopher2015-03-123-55/+68
| | | | | | | classes. Replace it with a cache to the TargetMachine and use that where applicable at the moment. llvm-svn: 232002
* Move the DataLayout to the generic TargetMachine, making it mandatory.Mehdi Amini2015-03-122-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: I don't know why every singled backend had to redeclare its own DataLayout. There was a virtual getDataLayout() on the common base TargetMachine, the default implementation returned nullptr. It was not clear from this that we could assume at call site that a DataLayout will be available with each Target. Now getDataLayout() is no longer virtual and return a pointer to the DataLayout member of the common base TargetMachine. I plan to turn it into a reference in a future patch. The only backend that didn't have a DataLayout previsouly was the CPPBackend. It now initializes the default DataLayout. This commit is NFC for all the other backends. Test Plan: clang+llvm ninja check-all Reviewers: echristo Subscribers: jfb, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8243 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 231987
* [PowerPC] Remove canFoldAsLoad from instruction definitionsHal Finkel2015-03-115-8/+8
| | | | | | | | | | | | | | | | | The PowerPC backend had a number of loads that were marked as canFoldAsLoad (and I'm partially at fault here for copying around the relevant line of TableGen definitions without really looking at what it meant). This is not right; PPC (non-memory) instructions don't support direct memory operands, and so there is nothing a 'foldable' instruction could be folded into. Noticed by inspection, no test case. The one thing we might lose by doing this is ability to fold some loads into stackmap/patchpoint pseudo-instructions. However, this was untested, and would not obviously have worked for extending loads, and I'd rather re-add support for that once it can be tested. llvm-svn: 231982
* Have getCallPreservedMask and getThisCallPreservedMask take aEric Christopher2015-03-114-5/+8
| | | | | | | MachineFunction argument so that we can grab subtarget specific features off of it. llvm-svn: 231979
* One more getCalleeSavedRegs prototype with nullptr.Eric Christopher2015-03-111-2/+1
| | | | llvm-svn: 231977
* Updated with list of possible improvements we are tracking internallyKit Barton2015-03-112-0/+40
| | | | llvm-svn: 231946
* Have TargetRegisterInfo::getLargestLegalSuperClass take aEric Christopher2015-03-102-5/+7
| | | | | | | MachineFunction argument so that it can look up the subtarget rather than using a cached one in some Targets. llvm-svn: 231888
* Remove the use of the subtarget in MCCodeEmitter creation andEric Christopher2015-03-102-11/+8
| | | | | | | update all ports accordingly. Required a couple of small rewrites in handling subtarget features during creation in PPC. llvm-svn: 231861
* Add support for part-word atomics for PPCNemanja Ivanovic2015-03-107-67/+141
| | | | | | http://reviews.llvm.org/D8090#inline-67337 llvm-svn: 231843
* Change the generation of the vmuluwm instruction to be based on the MUL opcode.Kit Barton2015-03-102-3/+9
| | | | | | Phabricator review: http://reviews.llvm.org/D8185 llvm-svn: 231827
* DataLayout is mandatory, update the API to reflect it with references.Mehdi Amini2015-03-103-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Now that the DataLayout is a mandatory part of the module, let's start cleaning the codebase. This patch is a first attempt at doing that. This patch is not exactly NFC as for instance some places were passing a nullptr instead of the DataLayout, possibly just because there was a default value on the DataLayout argument to many functions in the API. Even though it is not purely NFC, there is no change in the validation. I turned as many pointer to DataLayout to references, this helped figuring out all the places where a nullptr could come up. I had initially a local version of this patch broken into over 30 independant, commits but some later commit were cleaning the API and touching part of the code modified in the previous commits, so it seemed cleaner without the intermediate state. Test Plan: Reviewers: echristo Subscribers: llvm-commits From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 231740
* Remove the remaining uses of abs64 and nuke it.Benjamin Kramer2015-03-091-1/+1
| | | | | | std::abs works just fine and we're already using it in many places. NFC intended. llvm-svn: 231696
* Make constant arrays that are passed to functions as const.Benjamin Kramer2015-03-071-5/+2
| | | | | | | | In theory this allows the compiler to skip materializing the array on the stack. In practice clang often fails to do that, but that's a different story. NFC. llvm-svn: 231571
* Do not restrict interleaved unrolling to small loops, depending on the target.Olivier Sallenave2015-03-062-0/+5
| | | | llvm-svn: 231528
* Use the correct func begin symbol in all places in ppc.Rafael Espindola2015-03-051-2/+1
| | | | | | I missed an occurrence of the old symbol in my previous patch. llvm-svn: 231398
* Use the generic Lfunc_begin label on ppc.Rafael Espindola2015-03-052-5/+4
| | | | | | This removes yet another custom label to mark the start of a function. llvm-svn: 231390
* While reviewing the changes to Clang to add builtin support for the vsld, ↵Kit Barton2015-03-052-8/+18
| | | | | | vsrd, and vsrad instructions, it was pointed out that the builtins are generating the LLVM opcodes (shl, lshr, and ashr) not calls to the intrinsics. This patch changes the implementation of the vsld, vsrd, and vsrad instructions from from intrinsics to VXForm_1 instructions and makes them legal with P8 Altivec. It also removes the definition of the int_ppc_altivec_vsld, int_ppc_altivec_vsrd, and int_ppc_altivec_vsrad intrinsics. llvm-svn: 231378
* Add LLVM support for PPC cryptography builtinsNemanja Ivanovic2015-03-0410-1/+143
| | | | | | Review: http://reviews.llvm.org/D7955 llvm-svn: 231285
* Make DataLayout Non-Optional in the ModuleMehdi Amini2015-03-043-10/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: DataLayout keeps the string used for its creation. As a side effect it is no longer needed in the Module. This is "almost" NFC, the string is no longer canonicalized, you can't rely on two "equals" DataLayout having the same string returned by getStringRepresentation(). Get rid of DataLayoutPass: the DataLayout is in the Module The DataLayout is "per-module", let's enforce this by not duplicating it more than necessary. One more step toward non-optionality of the DataLayout in the module. Make DataLayout Non-Optional in the Module Module->getDataLayout() will never returns nullptr anymore. Reviewers: echristo Subscribers: resistor, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D7992 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 231270
* Test commit. Removed an unnecessary spaceNemanja Ivanovic2015-03-041-1/+1
| | | | llvm-svn: 231257
* [PowerPC] Remove unnecessary and incomplete commentaryBill Schmidt2015-03-041-412/+0
| | | | | | | | | | This "itinerary class map" in PPCSchedule.td is incomplete and redundant with the actual code. As it provides no value, we've decided to remove it. No functional change. llvm-svn: 231246
* Add the following 64-bit vector integer arithmetic instructions added in POWER8:Kit Barton2015-03-035-10/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | vaddudm vsubudm vmulesw vmulosw vmuleuw vmulouw vmuluwm vmaxsd vmaxud vminsd vminud vcmpequd vcmpequd. vcmpgtsd vcmpgtsd. vcmpgtud vcmpgtud. vrld vsld vsrd vsrad Phabricator review: http://reviews.llvm.org/D7959 llvm-svn: 231115
* Make some non-constant static variables non-static or fully const.Benjamin Kramer2015-03-011-34/+9
| | | | | | Otherwise we have to emit thread-safe initialization for them. NFC. llvm-svn: 230894
* [PowerPC] Fix PR22711 - Misaligned .toc sectionBill Schmidt2015-02-271-0/+1
| | | | | | | | | | | | Straightforward patch to emit an alignment directive when emitting a TOC entry. The test case was generated from the test in PR22711 that demonstrated a misaligned .toc section. The object code is run through llvm-readobj to verify that the correct alignment has been applied to the .toc section. Thanks to Ulrich Weigand for running down where the fix was needed. llvm-svn: 230801
* [PowerPC] Use vector types for memcpy and friends (sometimes)Hal Finkel2015-02-271-2/+25
| | | | | | | | | | When using Altivec, we can use vector loads and stores for aligned memcpy and friends. Starting with the P7 and VXS, we have reasonable unaligned vector stores. Starting with the P8, we have fast unaligned loads too. For QPX, we use vector loads are stores, but only for aligned memory accesses. llvm-svn: 230788
* getRegForInlineAsmConstraint wants to use TargetRegisterInfo forEric Christopher2015-02-262-10/+10
| | | | | | | | | a lookup, pass that in rather than use a naked call to getSubtargetImpl. This involved passing down and around either a TargetMachine or TargetRegisterInfo. Update all callers/definitions around the targets and SelectionDAG. llvm-svn: 230699
* Remove an argument-less call to getSubtargetImpl from TargetLoweringBase.Eric Christopher2015-02-261-1/+1
| | | | | | | | | This required plumbing a TargetRegisterInfo through computeRegisterProperties and into findRepresentativeClass which uses it for register class iteration. This required passing a subtarget into a few target specific initializations of TargetLowering. llvm-svn: 230583
* [PowerPC] Make LDtocL and friends invariant loadsHal Finkel2015-02-254-34/+54
| | | | | | | | | | | | | | | | | | | | | LDtocL, and other loads that roughly correspond to the TOC_ENTRY SDAG node, represent loads from the TOC, which is invariant. As a result, these loads can be hoisted out of loops, etc. In order to do this, we need to generate GOT-style MMOs for TOC_ENTRY, which requires treating it as a legitimate memory intrinsic node type. Once this is done, the MMO transfer is automatically handled for TableGen-driven instruction selection, and for nodes generated directly in PPCISelDAGToDAG, we need to transfer the MMOs manually. Also, we were not transferring MMOs associated with pre-increment loads, so do that too. Lastly, this fixes an exposed bug where R30 was not added as a defined operand of UpdateGBR. This problem was highlighted by an example (used to generate the test case) posted to llvmdev by Francois Pichet. llvm-svn: 230553
* [PowerPC] Cleanup unused target-specific SDAG nodesHal Finkel2015-02-254-35/+7
| | | | | | | | We had somehow accumulated a few target-specific SDAG nodes dealing with PPC64 TOC access that were referenced only in TableGen patterns. The associated (pseudo-)instructions are used, but are being generated directly. NFC. llvm-svn: 230518
* Silencing a "result of 32-bit shift implicitly converted to 64 bits (was ↵Aaron Ballman2015-02-251-1/+1
| | | | | | 64-bit shift intended?)" warning in MSVC; NFC. llvm-svn: 230489
* Silencing a -Wsign-compare warning triggered in MSVC; NFC.Aaron Ballman2015-02-251-1/+1
| | | | llvm-svn: 230488
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