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authorAaron Ballman <aaron@aaronballman.com>2015-02-25 13:05:24 +0000
committerAaron Ballman <aaron@aaronballman.com>2015-02-25 13:05:24 +0000
commit5561ed448b8da44f83d1c1cdb75f1266590372b1 (patch)
treeaf4dbec903d4a36a3b18d2265beee85fadb0798c /llvm/lib/Target/PowerPC
parent70c27ded97efa0d3b4df29ba3682f7e8abc1e683 (diff)
downloadbcm5719-llvm-5561ed448b8da44f83d1c1cdb75f1266590372b1.tar.gz
bcm5719-llvm-5561ed448b8da44f83d1c1cdb75f1266590372b1.zip
Silencing a "result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?)" warning in MSVC; NFC.
llvm-svn: 230489
Diffstat (limited to 'llvm/lib/Target/PowerPC')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 567cd2aa0e4..4f3a625633f 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -9987,7 +9987,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
isa<ConstantSDNode>(UI->getOperand(1)) &&
(cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
- (1 << Bits) == 0) {
+ (1ULL << Bits) == 0) {
SDNode *OtherAdd = *UI;
for (SDNode::use_iterator VI = OtherAdd->use_begin(),
VE = OtherAdd->use_end(); VI != VE; ++VI) {
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