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* Remove resetSubtargetFeatures as it is unused.Eric Christopher2014-09-032-21/+3
| | | | llvm-svn: 217071
* Add override to overriden virtual methods, remove virtual keywords.Benjamin Kramer2014-09-033-24/+8
| | | | | | No functionality change. Changes made by clang-tidy + some manual cleanup. llvm-svn: 217028
* Reinstate "Nuke the old JIT."Eric Christopher2014-09-0212-943/+24
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* Fix signed integer overflow in PPCInstPrinter.Alexey Samsonov2014-09-021-1/+1
| | | | | | This bug was reported by UBSan. llvm-svn: 216917
* [PowerPC] Guard against illegal selection of add for TargetConstant operandsHal Finkel2014-09-021-0/+7
| | | | | | | | | | | r208640 was reverted because it caused a self-hosting failure on ppc64. The underlying cause was the formation of ISD::ADD nodes with ISD::TargetConstant operands. Because we have no patterns for 'add' taking 'timm' nodes, these are selected as r+r add instructions (which is a miscompile). Guard against this kind of behavior in the future by making the backend crash should this occur (instead of silently generating invalid output). llvm-svn: 216897
* Remove 'virtual' keyword from methods markedwith 'override' keyword.Craig Topper2014-08-303-35/+32
| | | | llvm-svn: 216823
* Test commit. Fix whitespace from a previous patch of mine.Justin Hibbits2014-08-281-1/+1
| | | | llvm-svn: 216650
* Allow vectorization of division by uniform power of 2.Karthik Bhat2014-08-251-8/+10
| | | | | | | | This patch adds support to recognize division by uniform power of 2 and modifies the cost table to vectorize division by uniform power of 2 whenever possible. Updates Cost model for Loop and SLP Vectorizer.The cost table is currently only updated for X86 backend. Thanks to Hal, Andrea, Sanjay for the review. (http://reviews.llvm.org/D4971) llvm-svn: 216371
* [PowerPC] Add support for dcbtst and icbt (prefetch)Hal Finkel2014-08-232-1/+23
| | | | | | | | | | | | Adds code generation support for dcbtst (data cache prefetch for write) and icbt (instruction cache prefetch for read - Book E cores only). We still end up with a 'cannot select' error for the non-supported prefetch intrinsic forms. This will be fixed in a later commit. Fixes PR20692. llvm-svn: 216339
* name change: isPow2DivCheap -> isPow2SDivCheapSanjay Patel2014-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | isPow2DivCheap That name doesn't specify signed or unsigned. Lazy as I am, I eventually read the function and variable comments. It turns out that this is strictly about signed div. But I discovered that the comments are wrong: srl/add/sra is not the general sequence for signed integer division by power-of-2. We need one more 'sra': sra/srl/add/sra That's the sequence produced in DAGCombiner. The first 'sra' may be removed when dividing by exactly '2', but that's a special case. This patch corrects the comments, changes the name of the flag bit, and changes the name of the accessor methods. No functional change intended. Differential Revision: http://reviews.llvm.org/D5010 llvm-svn: 216237
* TableGen: allow use of uint64_t for available features mask.Tim Northover2014-08-181-3/+3
| | | | | | | | | | ARM in particular is getting dangerously close to exceeding 32 bits worth of possible subtarget features. When this happens, various parts of MC start to fail inexplicably as masks get truncated to "unsigned". Mostly just refactoring at present, and there's probably no way to test. llvm-svn: 215887
* [PowerPC] Mark fixed-offset byvals as pointed-to by IR valuesHal Finkel2014-08-161-2/+2
| | | | | | | | | | | | A byval object, even if allocated at a fixed offset (prescribed by the ABI) is pointed to by IR values. Most fixed-offset stack objects are not pointed-to by IR values, so the default is to assume this is not possible. However, we need to override the default in this case (instruction scheduling can cause miscompiles otherwise). Fixes PR20280. llvm-svn: 215795
* [PowerPC] Darwin byval arguments are not immutableHal Finkel2014-08-161-1/+1
| | | | | | | | | | | | On PPC/Darwin, byval arguments occur at fixed stack offsets in the callee's frame, but are not immutable -- the pointer value is directly available to the higher-level code as the address of the argument, and the value of the byval argument can be modified at the IR level. This is necessary, but not sufficient, to fix PR20280. When PR20280 is fixed in a follow-up commit, its test case will cover this change. llvm-svn: 215793
* Remove HasLEB128.Rafael Espindola2014-08-151-1/+0
| | | | | | We already require CFI, so it should be safe to require .leb128 and .uleb128. llvm-svn: 215712
* PPC: Clean up pointer casting, no functionality change.Benjamin Kramer2014-08-151-2/+2
| | | | | | Silences GCC's -Wcast-qual. llvm-svn: 215703
* [PPC64] Add missing dependency on X2 to LDinto_toc.Bill Schmidt2014-08-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LDinto_toc pattern has been part of 64-bit PowerPC for a long time, and represents loading from a memory location into the TOC register (X2). However, this pattern doesn't explicitly record that it modifies that register. This patch adds the missing dependency. It was very surprising to me that this has never shown up as a problem in the past, and that we only saw this problem recently in a single scenario when building a self-hosted clang. It turns out that in most cases we have another dependency present that keeps the LDinto_toc instruction tied in place. LDinto_toc is used for TOC restore following a call site, so this is a typical sequence: BCTRL8 <regmask>, %CTR8<imp-use>, %RM<imp-use>, %X3<imp-use>, %X12<imp-use>, %X1<imp-def>, ... LDinto_toc 24, %X1 ADJCALLSTACKUP 96, 0, %R1<imp-def>, %R1<imp-use> Because the LDinto_toc is inserted prior to the ADJCALLSTACKUP, there is a natural anti-dependency between the two that keeps it in place. Therefore we don't usually see a problem. However, in one particular case, one call is followed immediately by another call, and the second call requires a parameter that is a TOC-relative address. This is the code sequence: BCTRL8 <regmask>, %CTR8<imp-use>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X12<imp-use>, %X1<imp-def>, ... LDinto_toc 24, %X1 ADJCALLSTACKUP 96, 0, %R1<imp-def>, %R1<imp-use> ADJCALLSTACKDOWN 96, %R1<imp-def>, %R1<imp-use> %vreg39<def> = ADDIStocHA %X2, <ga:@.str>; G8RC_and_G8RC_NOX0:%vreg39 %vreg40<def> = ADDItocL %vreg39<kill>, <ga:@.str>; G8RC:%vreg40 G8RC_and_G8RC_NOX0:%vreg39 Note that the back-to-back stack adjustments are the same size! The back end is smart enough to recognize this and optimize them away: BCTRL8 <regmask>, %CTR8<imp-use>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X12<imp-use>, %X1<imp-def>, ... LDinto_toc 24, %X1 %vreg39<def> = ADDIStocHA %X2, <ga:@.str>; G8RC_and_G8RC_NOX0:%vreg39 %vreg40<def> = ADDItocL %vreg39<kill>, <ga:@.str>; G8RC:%vreg40 G8RC_and_G8RC_NOX0:%vreg39 Now there is nothing to prevent the ADDIStocHA instruction from moving ahead of the LDinto_toc instruction, and because of the longest-path heuristic, this is what happens. With the accompanying patch, %X2 is represented as an implicit def: BCTRL8 <regmask>, %CTR8<imp-use>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X12<imp-use>, %X1<imp-def>, ... LDinto_toc 24, %X1, %X2<imp-def,dead> ADJCALLSTACKUP 96, 0, %R1<imp-def,dead>, %R1<imp-use> ADJCALLSTACKDOWN 96, %R1<imp-def,dead>, %R1<imp-use> %vreg39<def> = ADDIStocHA %X2, <ga:@.str>; G8RC_and_G8RC_NOX0:%vreg39 %vreg40<def> = ADDItocL %vreg39<kill>, <ga:@.str>; G8RC:%vreg40 G8RC_and_G8RC_NOX0:%vreg39 So now when the two stack adjustments are removed, ADDIStocHA is prevented from being moved above LDinto_toc. I have not yet created a test case for this, because the original failure occurs on a relatively large function that needs reduction. However, this is a fairly serious bug, despite its infrequency, and I wanted to get this patch onto the list as soon as possible so that it can be considered for a 3.5 backport. I'll work on whittling down a test case. Have we missed the boat for 3.5 at this point? Thanks, Bill llvm-svn: 215685
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-1322-42/+47
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* [PowerPC] Implement PPCTargetLowering::getTgtMemIntrinsicHal Finkel2014-08-132-0/+80
| | | | | | | | | | | | | | | | | This implements PPCTargetLowering::getTgtMemIntrinsic for Altivec load/store intrinsics. As with the construction of the MachineMemOperands for the intrinsic calls used for unaligned load/store lowering, the only slight complication is that we need to represent a larger memory range than the loaded/stored value-type size (because the address is rounded down to an aligned address, and we need to conservatively represent the entire possible range of the actual access). This required adding an extra size field to TargetLowering::IntrinsicInfo, and this was done in a way that required no modifications to other targets (the size defaults to the store size of the provided memory data type). This fixes test/CodeGen/PowerPC/unal-altivec-wint.ll (so it can be un-XFAILed). llvm-svn: 215512
* @l and friends adjust their value depending the context used in.Joerg Sonnenberger2014-08-104-36/+142
| | | | | | | For ori, they are unsigned, for addi, signed. Create a new target expression type to handle this and evaluate Fixups accordingly. llvm-svn: 215315
* If available, pass down the Fixup object to EvaluateAsRelocatable.Joerg Sonnenberger2014-08-102-3/+5
| | | | | | | At least on PowerPC, the interpretation of certain modifiers depends on the context they appear in. llvm-svn: 215310
* Allow the third argument for the subi family to be an expression.Joerg Sonnenberger2014-08-091-8/+27
| | | | llvm-svn: 215286
* Use the full form of dccci and iccci from the early PPC 405 documents,Joerg Sonnenberger2014-08-091-15/+9
| | | | | | | since the operands are actually used on those cores. Provide aliases for the only documented case in the newer Power ISA speec. llvm-svn: 215282
* Initialize PPC DataLayout based on the Triple only.Eric Christopher2014-08-092-11/+12
| | | | llvm-svn: 215281
* Remove extraneous 64-bit argument to the PPC TargetMachine constructorEric Christopher2014-08-094-11/+13
| | | | | | and update initialization. llvm-svn: 215280
* Allow large immediates for branch instructions in 32bit mode.Joerg Sonnenberger2014-08-081-3/+17
| | | | llvm-svn: 215240
* Provide an implementation of getNoopForMachoTarget for PPC, otherwiseJoerg Sonnenberger2014-08-082-0/+7
| | | | | | empty functions will assert in the MC object writer. llvm-svn: 215238
* Add low-level option for avoiding float stores from va_start untilJoerg Sonnenberger2014-08-081-1/+7
| | | | | | soft-float is properly supported. llvm-svn: 215221
* Add support for SPE load/store from memory.Joerg Sonnenberger2014-08-085-0/+202
| | | | llvm-svn: 215220
* Temporarily Revert "Nuke the old JIT." as it's not quite ready toEric Christopher2014-08-0712-24/+903
| | | | | | | | | | | be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 215154
* Add the majority of the remaining SPE instructions.Joerg Sonnenberger2014-08-071-0/+319
| | | | llvm-svn: 215131
* Nuke the old JIT.Rafael Espindola2014-08-0712-903/+24
| | | | | | | | | I am sure we will be finding bits and pieces of dead code for years to come, but this is a good start. Thanks to Lang Hames for making MCJIT a good replacement! llvm-svn: 215111
* Add mfasr and mtasrJoerg Sonnenberger2014-08-071-0/+3
| | | | llvm-svn: 215110
* Add mfrtcu and mfrtcl instructionsJoerg Sonnenberger2014-08-071-0/+3
| | | | llvm-svn: 215109
* Support mttbl and mttbu mnemonicJoerg Sonnenberger2014-08-071-0/+3
| | | | llvm-svn: 215108
* Add RFID instruction.Joerg Sonnenberger2014-08-071-0/+2
| | | | llvm-svn: 215105
* Fix Itineray class of rfiJoerg Sonnenberger2014-08-071-1/+1
| | | | llvm-svn: 215104
* Spell e500 feature in lower case.Joerg Sonnenberger2014-08-071-1/+1
| | | | llvm-svn: 215103
* Add first bunch of SPE instructions. As they overlap with Altivec, markJoerg Sonnenberger2014-08-075-1/+78
| | | | | | | them as parser-only until the disassembler is extended to handle predicates properly. llvm-svn: 215102
* Remove the target machine from CCState. Previously it was only usedEric Christopher2014-08-063-18/+23
| | | | | | | | | to get the subtarget and that's accessible from the MachineFunction now. This helps clear the way for smaller changes where we getting a subtarget will require passing in a MachineFunction/Function as well. llvm-svn: 214988
* Remove a virtual function from TargetMachine. NFC.Rafael Espindola2014-08-051-1/+0
| | | | llvm-svn: 214929
* [PowerPC] Swap arguments and adjust shift count for vsldoi on little endianBill Schmidt2014-08-053-16/+41
| | | | | | | | | | | | | | Commits r213915 and r214718 fix recognition of shuffle masks for vmrg* and vpku*um instructions for a little-endian target, by swapping the input arguments. The vsldoi instruction requires similar treatment, and also needs its shift count adjusted for little endian. Reviewed by Ulrich Weigand. This is a bug fix candidate for release 3.5 (and hopefully the last of those for PowerPC). llvm-svn: 214923
* Add accessors for the PPC 403 bank registers.Joerg Sonnenberger2014-08-051-0/+9
| | | | llvm-svn: 214875
* Accessors for SSR2 and SSR3 on PPC 403.Joerg Sonnenberger2014-08-051-0/+6
| | | | llvm-svn: 214867
* Add dci/ici instructions for PPC 476 and friends.Joerg Sonnenberger2014-08-051-0/+16
| | | | llvm-svn: 214864
* Add mftblo and mftbhi for PPC 4xx.Joerg Sonnenberger2014-08-051-0/+5
| | | | llvm-svn: 214863
* Add lswi / stswi for assembler use with a warning to not add patternsJoerg Sonnenberger2014-08-051-0/+10
| | | | | | for them. llvm-svn: 214862
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-055-64/+42
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Add TCR register accessJoerg Sonnenberger2014-08-041-0/+3
| | | | llvm-svn: 214826
* Add PPC 603's tlbld and tlbli instructions.Joerg Sonnenberger2014-08-041-0/+5
| | | | llvm-svn: 214825
* [PPC64LE] Fix wrong IR for vec_sld and vec_vsldoiBill Schmidt2014-08-041-30/+12
| | | | | | | | | | | | | | | My original LE implementation of the vsldoi instruction, with its altivec.h interfaces vec_sld and vec_vsldoi, produces incorrect shufflevector operations in the LLVM IR. Correct code is generated because the back end handles the incorrect shufflevector in a consistent manner. This patch and a companion patch for Clang correct this problem by removing the fixup from altivec.h and the corresponding fixup from the PowerPC back end. Several test cases are also modified to reflect the now-correct LLVM IR. llvm-svn: 214800
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