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* Always compute all the bits in ComputeMaskedBits.Rafael Espindola2012-04-043-17/+5
| | | | | | | | This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
* Make PPCCompilationCallbackC function to be static, so there will be no need ↵Anton Korobeynikov2012-04-031-3/+5
| | | | | | | | to issue call via PLT when LLVM is built as shared library. This mimics the X86 backend towards the approach. llvm-svn: 153938
* The binutils for the IBM BG/P are too old to support CFI.Hal Finkel2012-04-022-0/+6
| | | | llvm-svn: 153886
* Implement the SVR4 byval alignment for aggregates. Fixing a FIXME.Roman Divacky2012-04-021-1/+10
| | | | llvm-svn: 153876
* Move getOpcodeName from the various target InstPrinters into the superclass ↵Benjamin Kramer2012-04-022-5/+0
| | | | | | | | MCInstPrinter. All implementations used the same code. llvm-svn: 153866
* Remove getInstructionName from MCInstPrinter implementations in favor of ↵Craig Topper2012-04-022-4/+2
| | | | | | using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. llvm-svn: 153863
* Make MCInstrInfo available to the MCInstPrinter. This will be used to remove ↵Craig Topper2012-04-022-4/+5
| | | | | | getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. llvm-svn: 153860
* Fix some 80-col. violations I introduced with the A2 PPC64 core.Hal Finkel2012-04-012-63/+126
| | | | llvm-svn: 153852
* Enable prefetch generation on PPC64.Hal Finkel2012-04-012-0/+6
| | | | llvm-svn: 153851
* Add LdStSTD* itin. for the PPC64 A2 core.Hal Finkel2012-04-011-0/+20
| | | | llvm-svn: 153850
* Set the default PPC node scheduling preference to ILP (for the embedded cores).Hal Finkel2012-04-012-0/+10
| | | | | | | The 440 and A2 cores have detailed itineraries, and this allows them to be fully used to maximize throughput. llvm-svn: 153845
* Add ppc440 itin. entries for LdStSTD*Hal Finkel2012-04-011-0/+20
| | | | llvm-svn: 153844
* Use full anti-dep. breaking with post-ra sched. on the embedded ppc cores.Hal Finkel2012-04-011-2/+3
| | | | | | | | | | | Post-RA scheduling gives a significant performance improvement on the embedded cores, so turn it on. Using full anti-dep. breaking is important for FP-intensive blocks, so turn it on (just on the embedded cores for now; this should also be good on the 970s because post-ra scheduling is all that we have for now, but that should have more testing first). llvm-svn: 153843
* Add instruction itinerary for the PPC64 A2 core.Hal Finkel2012-04-017-4/+582
| | | | | | | This adds a full itinerary for IBM's PPC64 A2 embedded core. These cores form the basis for the CPUs in the new IBM BG/Q supercomputer. llvm-svn: 153842
* Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore.Hal Finkel2012-04-019-107/+140
| | | | | | | | | | | Loads and stores can have different pipeline behavior, especially on embedded chips. This change allows those differences to be expressed. Except for the 440 scheduler, there are no functionality changes. On the 440, the latency adjustment is only by one cycle, and so this probably does not affect much. Nevertheless, it will make a larger difference in the future and this removes a FIXME from the 440 itin. llvm-svn: 153821
* Fix dynamic linking on PPC64.Hal Finkel2012-03-318-35/+126
| | | | | | | | | | | | | | | | | | Dynamic linking on PPC64 has had problems since we had to move the top-down hazard-detection logic post-ra. For dynamic linking to work there needs to be a nop placed after every call. It turns out that it is really hard to guarantee that nothing will be placed in between the call (bl) and the nop during post-ra scheduling. Previous attempts at fixing this by placing logic inside the hazard detector only partially worked. This is now fixed in a different way: call+nop codegen-only instructions. As far as CodeGen is concerned the pair is now a single instruction and cannot be split. This solution works much better than previous attempts. The scoreboard hazard detector is also renamed to be more generic, there is currently no cpu-specific logic in it. llvm-svn: 153816
* Remove unnecessary llvm:: qualificationsCraig Topper2012-03-271-1/+1
| | | | llvm-svn: 153500
* Prune some includes and forward declarations.Craig Topper2012-03-261-0/+1
| | | | llvm-svn: 153429
* Fix small-integer VAARG on SVR4 ABI PPC64.Hal Finkel2012-03-241-5/+17
| | | | | | | The PPC64 SVR4 ABI requires integer stack arguments, and thus the var. args., that are smaller than 64 bits be zero extended to 64 bits. llvm-svn: 153373
* PPC::DBG_VALUE must use Reg+Imm frame-index elimination even for large ↵Hal Finkel2012-03-221-1/+2
| | | | | | | | offsets. Fixes PR12203. I don't have a small test case yet, but I'll try to construct one. llvm-svn: 153240
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-1710-21/+16
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Convert more static tables of registers used by calling convention to ↵Craig Topper2012-03-111-4/+4
| | | | | | uint16_t to reduce space. llvm-svn: 152538
* Use uint16_t to store registers and opcode in static tables in the target ↵Craig Topper2012-03-112-13/+13
| | | | | | specific backends. llvm-svn: 152537
* Convert PowerPC to register mask operands.Roman Divacky2012-03-066-122/+52
| | | | llvm-svn: 152122
* Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach2012-03-052-3/+5
| | | | | | | Used to allow context sensitive printing of super-register or sub-register references. llvm-svn: 152043
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-042-6/+6
| | | | | | size of static data. llvm-svn: 151996
* Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng2012-02-282-14/+15
| | | | | | direct call. llvm-svn: 151645
* Properly MCize the section switch, removing a FIXME.Roman Divacky2012-02-281-2/+4
| | | | llvm-svn: 151639
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-282-15/+14
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. llvm-svn: 151630
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-282-14/+15
| | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 llvm-svn: 151623
* Reapply r151278 with fixes.Roman Divacky2012-02-271-6/+16
| | | | | | MCize function entry label emission on PowerPC64 properly. llvm-svn: 151547
* Revert r151278, breaks static linking.Hal Finkel2012-02-251-14/+6
| | | | | | | | | Reverting this because it breaks static linking on ppc64. Specifically, it may be linkonce_odr functions that are the problem. With this patch, if you link statically, calls to some functions end up calling their descriptor addresses instead of calling to their entry points. This causes the execution to fail with SIGILL (b/c the descriptor address just has some pointers, not code). llvm-svn: 151433
* X11/X2 loads around indirect calls on ppc64 should not be deleted.Hal Finkel2012-02-241-2/+4
| | | | llvm-svn: 151374
* MCize function entry label emission on PowerPC64 properly.Roman Divacky2012-02-231-6/+14
| | | | llvm-svn: 151278
* Allow the use of an alternate symbol for calculating a function's size.Hal Finkel2012-02-221-1/+5
| | | | | | | | | | | | | The standard function epilog includes a .size directive, but ppc64 uses an alternate local symbol to tag the actual start of each function. Until recently, binutils accepted the .size directive as: .size test1, .Ltmp0-test1 however, using this directive with recent binutils will result in the error: .size expression for XXX does not evaluate to a constant so we must use the label which actually tags the start of the function. llvm-svn: 151200
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-221-1/+1
| | | | | | to static data that should not be modified. llvm-svn: 151134
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-1834-62/+62
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Move pass configuration out of pass constructors: BranchFolderPassAndrew Trick2012-02-081-6/+7
| | | | llvm-svn: 150095
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-074-8/+6
| | | | llvm-svn: 149961
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-051-0/+1
| | | | llvm-svn: 149814
* TargetPassConfig: confine the MC configuration to TargetMachine.Andrew Trick2012-02-042-8/+5
| | | | | | | | | | Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. llvm-svn: 149754
* Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick2012-02-032-10/+33
| | | | | | | | | | | Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. llvm-svn: 149672
* whitespaceAndrew Trick2012-02-032-9/+9
| | | | llvm-svn: 149671
* Widen the instruction encoder that TblGen emits to a 64 bits, which should ↵Owen Anderson2012-01-242-2/+2
| | | | | | accomodate every target I can think of offhand. llvm-svn: 148833
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-202-2/+0
| | | | llvm-svn: 148578
* Remove a bunch of unused variable assignments.Benjamin Kramer2012-01-201-2/+1
| | | | | | Found by the clang static analyzer. llvm-svn: 148541
* Ignore register mask operands when lowering instructions to MC.Jakob Stoklund Olesen2012-01-181-0/+2
| | | | | | | This is similar to implicit register operands. MC doesn't understand register liveness and call clobbers. llvm-svn: 148437
* Tidy up. 80 columns.Jim Grosbach2012-01-181-13/+13
| | | | llvm-svn: 148401
* Tidy up. MCAsmBackend naming conventions.Jim Grosbach2012-01-181-7/+7
| | | | llvm-svn: 148400
* Cleanup PPC RLWINM8 vs RLWINMHal Finkel2012-01-161-1/+1
| | | | | | No test case: output assembly will be identical. llvm-svn: 148261
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