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* Added getTargetLowering() to TargetMachine. Refactored targets to support this.Evan Cheng2006-03-138-13/+30
| | | | llvm-svn: 26742
* For functions that use vector registers, save VRSAVE, mark usedChris Lattner2006-03-134-10/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | registers, and update it on entry to each function, then restore it on exit. This compiles: void func(vfloat *a, vfloat *b, vfloat *c) { *a = *b * *c + *c; } to this: _func: mfspr r2, 256 oris r6, r2, 49152 mtspr 256, r6 lvx v0, 0, r5 lvx v1, 0, r4 vmaddfp v0, v1, v0, v0 stvx v0, 0, r3 mtspr 256, r2 blr GCC produces this (which has additional stack accesses): _func: mfspr r0,256 stw r0,-4(r1) oris r0,r0,0xc000 mtspr 256,r0 lvx v0,0,r5 lvx v1,0,r4 lwz r12,-4(r1) vmaddfp v0,v0,v1,v0 stvx v0,0,r3 mtspr 256,r12 blr llvm-svn: 26733
* Fix a couple of bugs that broke the alpha tester buildChris Lattner2006-03-131-2/+2
| | | | llvm-svn: 26722
* Handle cracked instructions in dispatch group formation.Chris Lattner2006-03-132-15/+28
| | | | llvm-svn: 26721
* Mark instructions that are cracked by the PPC970 decoder as such.Chris Lattner2006-03-134-26/+37
| | | | llvm-svn: 26720
* Several big changes:Chris Lattner2006-03-127-213/+317
| | | | | | | | | | | 1. Use flags on the instructions in the .td file to indicate the PPC970 unit type instead of a table in the .cpp file. Much cleaner. 2. Change the hazard recognizer to build d-groups according to the actual algorithm used, not my flawed understanding of it. 3. Model "must be in the first slot" and "must be the only instr in a group" accurately. llvm-svn: 26719
* blr is a branch tooChris Lattner2006-03-111-0/+1
| | | | llvm-svn: 26710
* teach the JIT to encode vector registersChris Lattner2006-03-101-32/+32
| | | | llvm-svn: 26697
* Change the interface for getting a target HazardRecognizer to be more clean.Chris Lattner2006-03-083-11/+8
| | | | llvm-svn: 26608
* add a noteChris Lattner2006-03-081-0/+41
| | | | llvm-svn: 26605
* Use "llvm.metadata" section for debug globals. Filter out these globals in theJim Laskey2006-03-071-1/+1
| | | | | | asm printer. llvm-svn: 26599
* add another missing store.Chris Lattner2006-03-071-0/+2
| | | | llvm-svn: 26595
* add a couple more load/store instrs, add a newline to the end of file.Chris Lattner2006-03-072-2/+17
| | | | llvm-svn: 26594
* This kinda sorta implements "things that have to lead a dispatch group".Nate Begeman2006-03-072-17/+42
| | | | llvm-svn: 26591
* add some new instructions to the classifier. With this, we correctly insertChris Lattner2006-03-071-0/+11
| | | | | | a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%). llvm-svn: 26590
* add some comments that describe what we modelChris Lattner2006-03-071-3/+18
| | | | llvm-svn: 26588
* Implement a very very simple hazard recognizer for LSU rejects and ctr set/readChris Lattner2006-03-073-2/+292
| | | | | | flushes llvm-svn: 26587
* add a noteChris Lattner2006-03-071-0/+14
| | | | llvm-svn: 26585
* implement TII::insertNoopChris Lattner2006-03-053-1/+8
| | | | llvm-svn: 26562
* Copysign needs to be expanded everywhere. Note that Alpha and IA64 shouldChris Lattner2006-03-051-0/+3
| | | | | | implement copysign as a native op if they have it. llvm-svn: 26541
* Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668.Chris Lattner2006-03-011-18/+59
| | | | llvm-svn: 26450
* add a noteChris Lattner2006-03-011-0/+18
| | | | llvm-svn: 26448
* Compile this:Chris Lattner2006-03-015-13/+42
| | | | | | | | | | | | | | | | | | | | | | | | | void foo(float a, int *b) { *b = a; } to this: _foo: fctiwz f0, f1 stfiwx f0, 0, r4 blr instead of this: _foo: fctiwz f0, f1 stfd f0, -8(r1) lwz r2, -4(r1) stw r2, 0(r4) blr This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the right thing for GCC bugzilla 26505. llvm-svn: 26447
* Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.Chris Lattner2006-03-013-25/+42
| | | | llvm-svn: 26445
* Vector op lowering.Evan Cheng2006-03-011-0/+16
| | | | llvm-svn: 26438
* Add a subtarget feature for the stfiwx instruction. I know the G5 has it,Chris Lattner2006-02-282-2/+6
| | | | | | | but I don't know what other PPC impls do. If someone could update the proc table, I would appreciate it :) llvm-svn: 26421
* remove implemented itemChris Lattner2006-02-281-17/+0
| | | | llvm-svn: 26418
* readme updatesNate Begeman2006-02-271-21/+26
| | | | llvm-svn: 26405
* Add memory printing support for PPC. Input memory operands now work withChris Lattner2006-02-241-1/+12
| | | | | | inline asms! :) llvm-svn: 26365
* Implement selection of inline asm memory operandsChris Lattner2006-02-241-0/+29
| | | | llvm-svn: 26348
* PPC JIT relocation model should be DynamicNoPIC.Evan Cheng2006-02-231-2/+2
| | | | llvm-svn: 26338
* Implement the PPC inline asm "L" modifier. This allows us to compile:Chris Lattner2006-02-231-4/+28
| | | | | | | | | | | | long long test(long long X) { __asm__("foo %0 %L0 %1 %L1" : "=r"(X): "r"(X)); return X; } to: foo r2 r3 r2 r3 llvm-svn: 26333
* - Added option -relocation-model to set relocation model. Valid values ↵Evan Cheng2006-02-226-21/+21
| | | | | | | | | | include static, pic, dynamic-no-pic, and default. PPC and x86 default is dynamic-no-pic for Darwin, pic for others. - Removed options -enable-pic and -ppc-static. llvm-svn: 26315
* Coordinate activities with llvm-gcc4 and dwarf.Jim Laskey2006-02-221-12/+11
| | | | llvm-svn: 26314
* split register class handling from explicit physreg handling.Chris Lattner2006-02-222-6/+5
| | | | llvm-svn: 26308
* Updates to match change of getRegForInlineAsmConstraint prototypeChris Lattner2006-02-212-3/+5
| | | | llvm-svn: 26305
* Moved PICEnabled to include/llvm/Target/TargetOptions.hEvan Cheng2006-02-184-1/+3
| | | | llvm-svn: 26272
* kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBCNate Begeman2006-02-172-83/+14
| | | | | | | and SUBE nodes that actually expose what's going on and allow for significant simplifications in the targets. llvm-svn: 26255
* If the false case is the current basic block, then this is a self loop.Evan Cheng2006-02-161-11/+0
| | | | | | | | | | We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra instruction in the loop. Instead, invert the condition and emit "Loop: ... br!cond Loop; br Out. Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering. llvm-svn: 26231
* If we have zero initialized data with external linkage, use .zerofill toChris Lattner2006-02-141-4/+11
| | | | | | | | | | | | | emit it (instead of .space), saving a bit of space in the .o file. For example: int foo[100]; int bar[100] = {}; when compiled with C++ or -fno-common results in shrinkage from 1160 to 360 bytes of space. The X86 backend can also do this on darwin. llvm-svn: 26185
* Make sure that weak functions are aligned properlyChris Lattner2006-02-141-2/+1
| | | | llvm-svn: 26181
* Switch to using getCALLSEQ_START instead of using our own creation callsChris Lattner2006-02-131-4/+4
| | | | llvm-svn: 26142
* Add missing patterns for andi. and andis., fixing test/Regression/CodeGen/Nate Begeman2006-02-121-2/+4
| | | | | | PowerPC/and-imm.ll llvm-svn: 26136
* Match getTargetNode() changes (now return SDNode* instead of SDOperand).Evan Cheng2006-02-091-68/+79
| | | | llvm-svn: 26085
* Change Select() fromEvan Cheng2006-02-091-80/+133
| | | | | | | | SDOperand Select(SDOperand N); to void Select(SDOperand &Result, SDOperand N); llvm-svn: 26067
* Darwin doesn't support #APP/#NO_APPChris Lattner2006-02-081-2/+2
| | | | llvm-svn: 26066
* Rename BSel -> PPCBSel for the benefit of doxygen users.Chris Lattner2006-02-081-105/+115
| | | | | | | | Move the methods out of line. Remove unused Debug.h stuff. Teach getNumBytesForInstruction to know the size of an inline asm. llvm-svn: 26064
* Emit the 'mr' pseudoop for easier reading.Chris Lattner2006-02-081-0/+9
| | | | llvm-svn: 26053
* Move emails from nate into public placesChris Lattner2006-02-081-0/+17
| | | | llvm-svn: 26051
* Implement getConstraintType for PPC.Chris Lattner2006-02-072-0/+18
| | | | llvm-svn: 26042
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