split register class handling from explicit physreg handling.

llvm-svn: 26308

2 files changed, 5 insertions, 6 deletions

diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 243c51d7c9d..003d16c26b1 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -999,8 +999,8 @@ PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
 
 
 std::vector<unsigned> PPCTargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint,
-                             MVT::ValueType VT) const {
+getRegClassForInlineAsmConstraint(const std::string &Constraint,
+                                  MVT::ValueType VT) const {
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {      // GCC RS6000 Constraint Letters
     default: break;  // Unknown constriant letter
@@ -1051,8 +1051,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint,
     }
   }
   
-  // Handle explicit register names.
-  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
+  return std::vector<unsigned>();
 }
 
 // isOperandValidForConstraint
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index a1ce5545c32..86264aec38b 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -99,8 +99,8 @@ namespace llvm {
     
     ConstraintType getConstraintType(char ConstraintLetter) const;
     std::vector<unsigned> 
-      getRegForInlineAsmConstraint(const std::string &Constraint,
-                                   MVT::ValueType VT) const;
+      getRegClassForInlineAsmConstraint(const std::string &Constraint,
+                                        MVT::ValueType VT) const;
     bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
   };
 }