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* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-155-40/+0
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. llvm-svn: 48380
* Implement the real calling convention for ppc32 Altivec:Dale Johannesen2008-03-141-21/+118
| | | | | | | vectors go at the end of the memory area, after all non-vector parameters. llvm-svn: 48364
* Do not promote float params to double in varargsDale Johannesen2008-03-121-6/+0
| | | | | | | | | calls here. This was done earlier for params in the varargs part of the params; any float params that survive to here are in the non-varargs part, and must not be promoted. llvm-svn: 48310
* One more bit of Altivec parameter passing.Dale Johannesen2008-03-121-3/+5
| | | | llvm-svn: 48269
* Implement Altivec passing to varargs functions on ppc.Dale Johannesen2008-03-121-7/+72
| | | | llvm-svn: 48264
* Use PassManagerBase instead of FunctionPassManager for functionsDan Gohman2008-03-113-11/+10
| | | | | | | | that merely add passes. This allows them to be used with either FunctionPassManager or PassManager, or even with a custom new kind of pass manager. llvm-svn: 48256
* Generalize ExpandIntToFP to handle the case where the operand is legalDan Gohman2008-03-111-0/+4
| | | | | | | | and it's the result that requires expansion. This code is a little confusing because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type (the integer type) rather than the result type. llvm-svn: 48206
* Disable prolog code that aligns the stack when aDale Johannesen2008-03-101-7/+17
| | | | | | | | | | | | | | local object of >16 byte alignment exists. It does not work and getting it to work is not trivial, as explained in the comment. This fixes all the remaining ppc32 failures in the struct-layout-1 part of the gcc testsuite. (gcc does not support this either, and the only way to get such an object is with __attribute__((aligned)) or generic vectors; it can't be done in a standard-conforming program, or with Altivec. So I think disabling it is OK.) llvm-svn: 48188
* Change the "enable/disable" mechanism so that we can enable PPC registerBill Wendling2008-03-103-58/+77
| | | | | | scavenging for 32-bit and 64-bit separately. llvm-svn: 48186
* Default ISD::PREFETCH to expand.Evan Cheng2008-03-101-1/+0
| | | | llvm-svn: 48169
* fix 80 col violations.Chris Lattner2008-03-101-8/+8
| | | | llvm-svn: 48166
* Stylistic modifications. No functionality changes.Nicolas Geoffray2008-03-101-44/+39
| | | | llvm-svn: 48158
* Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC'sScott Michel2008-03-102-1/+10
| | | | | | | | return ValueType can depend its operands' ValueType. This is a cosmetic change, no functionality impacted. llvm-svn: 48145
* Add description of individual bits in CR. This fix PR1765.Nicolas Geoffray2008-03-105-38/+152
| | | | llvm-svn: 48143
* Increase ISD::ParamFlags to 64 bits. Increase the ByValSizeDale Johannesen2008-03-101-7/+13
| | | | | | | | | | field to 32 bits, thus enabling correct handling of ByVal structs bigger than 0x1ffff. Abstract interface a bit. Fixes gcc.c-torture/execute/pr23135.c and gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing on ppc32, quietly producing wrong code on x86-32.) llvm-svn: 48122
* Darwin PPC64 indirect call target goes in X12, not R12. This fixes theseChris Lattner2008-03-091-2/+3
| | | | | | | | two regression tests: test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll llvm-svn: 48120
* More ppc32 byval handling (bug fixes). ThingsDale Johannesen2008-03-081-3/+23
| | | | | | are looking pretty good now. llvm-svn: 48043
* Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} ↵Evan Cheng2008-03-081-0/+1
| | | | | | and prefetchnta instructions. llvm-svn: 48042
* Add support for calls with i128 return values on ppc64.Dan Gohman2008-03-081-3/+13
| | | | llvm-svn: 48041
* PPC64 passes arguments of integral type in i64 registers, not i32. Reflect thisBill Wendling2008-03-071-26/+43
| | | | | | | by promoting smaller integral values (i32 at this point) to i64, then truncating to get the wanted size. llvm-svn: 48030
* Add support for lowering 128-bit shifts on ppc64.Dan Gohman2008-03-071-44/+60
| | | | llvm-svn: 48029
* Next bits of PPC byval handling. Basically functionalDale Johannesen2008-03-071-7/+73
| | | | | | but there are bugs. llvm-svn: 48028
* Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).Chris Lattner2008-03-072-6/+16
| | | | llvm-svn: 48027
* Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to workChris Lattner2008-03-071-6/+3
| | | | | | with 32 or 64-bit operands/results. llvm-svn: 48026
* Next bit of PPC ByVal handling; call-site code seemsDale Johannesen2008-03-051-3/+11
| | | | | | correct now. llvm-svn: 47978
* Removed spurious EnablePPCRS check.Bill Wendling2008-03-041-4/+3
| | | | llvm-svn: 47918
* Move PPC lowering functions into PPCTargetLoweringDale Johannesen2008-03-042-28/+120
| | | | | | | class (cosmetic). First piece of byval implementation; this doesn't work yet. No functional change. llvm-svn: 47917
* Use a command-line option to turn register scavenging on/off for PPC.Bill Wendling2008-03-042-39/+51
| | | | llvm-svn: 47915
* This is the initial check-in for adding register scavenging to PPC. (Currently,Bill Wendling2008-03-035-104/+365
| | | | | | | | | PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that it uses a register other than the default R0 register (the scavenger scrounges for one). A significant part of this patch fixes how kill information is handled. llvm-svn: 47863
* add a noteChris Lattner2008-03-021-0/+39
| | | | llvm-svn: 47830
* Evan implemented this.Chris Lattner2008-03-021-23/+0
| | | | llvm-svn: 47827
* Use enumeration for preffered EH dwarf encoding reasonAnton Korobeynikov2008-02-292-6/+8
| | | | llvm-svn: 47770
* Interface of getByValTypeAlignment differed betweenDale Johannesen2008-02-282-0/+16
| | | | | | | | generic & x86 versions; change generic to follow x86 and improve comments. Add PPC version (not right for non-Darwin.) llvm-svn: 47734
* Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to ↵Evan Cheng2008-02-281-2/+2
| | | | | | 16-byte boundaries. llvm-svn: 47703
* EHPreferredDataFormat hook for PPC targets. Looks like DarwinAnton Korobeynikov2008-02-272-1/+30
| | | | | | uses the same encoding everywhere. Linux FIXME'ed. llvm-svn: 47701
* Don't hard-code the mask size to be 32, which is incorrect on ppc64Dan Gohman2008-02-271-3/+5
| | | | | | | and was causing aborts with the new APInt changes. This may also be fixing an obscure ppc64 bug. llvm-svn: 47692
* Final de-tabification.Bill Wendling2008-02-271-3/+3
| | | | llvm-svn: 47663
* Convert the last remaining users of the non-APInt form ofDan Gohman2008-02-272-16/+24
| | | | | | | ComputeMaskedBits to use the APInt form, and remove the non-APInt form. llvm-svn: 47654
* Rename PrintableName to Name.Bill Wendling2008-02-261-1/+1
| | | | llvm-svn: 47629
* Change "Name" to "AsmName" in the target register info. Gee, a refactoring toolBill Wendling2008-02-262-2/+2
| | | | | | would have been a Godsend here! llvm-svn: 47625
* Some platforms use the same name for 32-bit and 64-bit registers (likeBill Wendling2008-02-241-34/+35
| | | | | | | | | %r3 on PPC) in their ASM files. However, it's hard for humans to read during debugging. Adding a new field to the register data that lets you specify a different name to be printed than the one that goes into the ASM file -- %x3 instead of %r3, for instance. llvm-svn: 47534
* Remove bunch of gcc 4.3-related warnings from TargetAnton Korobeynikov2008-02-202-3/+4
| | | | llvm-svn: 47369
* I cannot find a libgcc function for this builtin. Therefor expanding it to ↵Andrew Lenharth2008-02-161-1/+2
| | | | | | a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support. llvm-svn: 47213
* Handle \n's in value names for more targets. The asm printers Chris Lattner2008-02-151-6/+21
| | | | | | really really really need refactoring :( llvm-svn: 47171
* Cosmetics.Dale Johannesen2008-02-151-6/+3
| | | | llvm-svn: 47168
* Remove warning about 64-bit code on processorDale Johannesen2008-02-151-4/+0
| | | | | | that doesn't support it. Per Chris. llvm-svn: 47162
* Rewrite tblgen handling of subtarget features soDale Johannesen2008-02-143-0/+3
| | | | | | | | | | it follows the order of the enum, not alphabetical. The motivation is to make -mattr=+ssse3,+sse41 select SSE41 as it ought to. Added "ignored" enum values of 0 to PPC and SPU to avoid compiler warnings. llvm-svn: 47143
* Change how FP immediates are handled. Nate Begeman2008-02-141-3/+0
| | | | | | | | | | | | | | 1) ConstantFP is now expand by default 2) ConstantFP is not turned into TargetConstantFP during Legalize if it is legal. This allows ConstantFP to be handled like Constant, allowing for targets that can encode FP immediates as MachineOperands. As a bonus, fix up Itanium FP constants, which now correctly match, and match more constants! Hooray. llvm-svn: 47121
* Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBitsDan Gohman2008-02-132-2/+2
| | | | | | to pass the mask APInt by value, not by reference. llvm-svn: 47096
* Enable exception handling int JITNicolas Geoffray2008-02-131-0/+11
| | | | llvm-svn: 47079
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